DELAY CHAIN BURN-IN FOR INCREASED REPEATABILITY OF PHYSICALLY UNCLONABLE FUNCTIONS

• US 20120081143A1
• Filed: 10/05/2010
• Published: 04/05/2012
• Est. Priority Date: 10/05/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Behrends, Derick Gardner, Christensen, Todd Alan, Hebig, Travis Reynold, Nelson, Daniel Mark
• Granted Patent: US 8,159,260 B1
• Time in Patent Office: Days
• US Class Current: 326/8
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 9/0866 involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics

Abstract

A circuit and method increases the repeatability of physically undetectable functions (PUFs) by enhancing the variation of signal delay through two delay chains during chip burn-in. A burn-in circuit holds the inputs of the two delay chains at opposite random values during the burn-in process. All the PFETs in the delay chains with a low value at the input will be burned in with a higher turn on voltage. Since the PFETs affected in the two delay chains are driven by opposite transitions at burn-in, alternating sets of delay components in the two delay chains are affected by the burn-in cycle. Under normal operation, both of the delay chains see the same input so only one chain has an increase in delay to achieve a statistically reliable difference in the two delay paths thereby increasing the overall repeatability of the PUF circuit.

Claims

1. ) An electronic circuit comprising:

a first delay chain and a second delay chain each having inputs and outputs;

a burn-in circuit that places the electronic circuit in a burn-in mode and places a random input bit on the input of the first delay chain and places an inverse of the random input bit on the input of the second delay chain and holds these inputs of the first and second delay chains while the circuit is burned in; and

an arbiter circuit connected to the outputs of the first and second delay chains to output a “

0”

or a “

1”

depending on which delay chain is faster when a challenge bit is applied at the inputs of first and second delay chains.

3. ) The electronic circuit of claim 1 wherein the outputs of the delay chains connected to the arbiter provide for a challenge/response of physically unclonable function.

4. ) The electronic circuit of claim 1 wherein the arbiter circuit is a latch that detects which of the first and second delay chains transitions first after receiving a challenge input.

5. ) The electronic circuit of claim 1 wherein the circuit burn-in includes burning-in an entire integrated circuit containing the first and second delay chains.

6. ) The electronic circuit of claim 1 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) inverters.

7. ) The electronic circuit of claim 1 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) NAND gates.

8. ) The electronic circuit of claim 1 wherein the burn-in circuit comprises:

a first and second NAND gate, with the first NAND gate having an output connected to the first delay chain, the second NAND gate having an output connected to the second delay chain, and a challenge_clk signal connected to a first input of the first and second NAND gates, wherein the output of the first and second NAND gates provide the random bit and the inverse of the random bit on the inputs of the delay chains;

a third and fourth NAND gate, with the third NAND gate having an output connected to a second input of the first NAND gate and the fourth NAND gate having an output connected to a second input of the second NAND gate;

a burn-in signal connected to a first input of the third and fourth NAND gates; and

a random data signal connected to a second input of the fourth NAND gate and connected to a second input of the third NAND gate through an inverter.

2. ) (canceled)

9. ) An electronic circuit comprising:

a first delay chain and a second delay chain each having inputs and outputs, wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) inverters;

a burn-in circuit that places the electronic circuit in a burn-in mode and places a random input bit on the input of the first delay chain and places an inverse of the random input bit on the input of the second delay chain and holds these inputs of the first and second delay chains while the circuit is burned in;

a latch connected to the outputs of the first and second delay chains to output a “

0”

or a “

1”

depending on which delay chain is faster when a challenge bit is applied at the inputs of first and second delay chains, wherein the outputs of the delay chains connected to the arbiter provide for a challenge/response of physically unclonable function;

wherein the burn-in circuit comprises;

a first and second NAND gate, with the first NAND gate having an output connected to the first delay chain, the second NAND gate having an output connected to the second delay chain, and a challenge_clk signal connected to a first input of the first and second NAND gates, wherein the output of the first and second NAND gates provide the random bit and the inverse of the random bit on the inputs of the delay chains;

a third and fourth NAND gate, with the third NAND gate having an output connected to a second input of the first NAND gate and the fourth NAND gate having an output connected to a second input of the second NAND gate;

a burn-in signal connected to a first input of the third and fourth NAND gates; and

a random data signal connected to a second input of the fourth NAND gate and connected to a second input of the third NAND gate through an inverter.

10. ) A method for increased repeatability in physically unclonable functions by increasing the delay difference of delay chains in an integrated circuit, the method comprising the steps of:

(A) generating a random bit;

(B) applying the random bit to an input of a first delay chain and an inverse of the random bit to an input of a second delay chain;

(C) performing burn-in on the first and second delay chains while maintaining the random bit and the inverse of the random bit at the inputs to the first and second delay chains; and

(D) using outputs of the delay chains connected to an arbiter for a challenge/response of physically unclonable function.

12. ) The method of claim 10 wherein the arbiter is a latch that detects which of the first and second delay chains transitions first after receiving a challenge input.

13. ) The method of claim 10 wherein the step of performing burn-in includes burning-in an entire integrated circuit containing the first and second delay chains.

14. ) The method of claim 10 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) inverters.

15. ) The method of claim 10 wherein the first and second delay chains are a chain of complementary metal-oxide semiconductor (CMOS) NAND gates.

11. ) (canceled)