SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR

• US 20120081977A1
• Filed: 09/26/2011
• Published: 04/05/2012
• Est. Priority Date: 10/04/2010
• Status: Active Grant

• Current Assignee: Yuniarto Widjaja, Zvi Or-Bach
• Original Assignee: Yuniarto Widjaja, Zvi Or-Bach
• Inventors: WIDJAJA, Yuniarto, Or-Bach, Zvi
• Granted Patent: US 8,194,471 B2
• Time in Patent Office: Days
• US Class Current: 365/189.011
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

Claims

1. A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells, the method comprising:

applying an electrical signal to buried regions of said memory cells,

wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and

wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.

2. The method of claim 1, wherein each of said memory cells further comprises a region of the second conductivity type at the surface.

3. The method of claim 1, wherein each of said memory cells further comprises a gate region above the surface and is insulated therefrom by an insulating layer.

4. The method of claim 1, wherein each of said memory cells further comprises a well region of the first conductivity type beneath the buried region.

5. The method of claim 1, wherein said electrical signal applied to said buried region comprises a pulse.

6. The method of claim 1, wherein said electrical signal applied to said buried region comprises a constant amplitude level.

7. The method of claim 1, wherein said holding operation is performed to a plurality of the memory cells in parallel.

8. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:

applying electrical signals to a buried region of a memory cell of said semiconductor memory array; and

causing a current to flow into said buried region, wherein the memory cell comprises;

a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

the buried region located beneath the surface of the memory cell, the buried region having a second conductivity type; and

a third region defining at least a further portion of the surface of the memory cell, the third region having the second conductivity type.

9. The method of claim 8, wherein said electrical signals applied to said buried region are of different amplitude or polarity, depending on an operation of said memory cell.

10. The method of claim 8, further comprising:

reading a state of the memory cell via said current flowing from said third region to said buried region.

11. The method of claim 8, wherein said current has an amplitude that is different when said memory cell is in a first data state than when said memory cell is in a second data state.

12. The method of claim 8, further comprising:

writing a first data state to said memory cell by injecting a charge to said floating body region via said current flowing from said third region into said buried region.

13. The method of claim 8, further comprising:

writing a second data state to said memory cell by removing a charge from said floating body region via said current flowing into said buried region.

14. The method of claim 8, further comprising:

applying the electrical signals of different amplitude or polarity to said third region depending on an operation of said memory cell.

15. The method of claim 8, wherein the memory cell further comprises a gate region above the surface and insulated therefrom by an insulating layer.

16. The method of claim 8, wherein the memory cell further comprises a well region of a first conductivity type beneath the buried region.

17. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:

applying electrical signals to a memory cell of the semiconductor memory array having at least one surface, wherein the memory cell comprises;

a floating body region having a first conductivity type, wherein a surface of the semiconductor memory array defines at least a portion of the floating body region;

a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type; and

a third region defining at least a further portion of the surface of the memory cell, said third region having the second conductivity type; and

causing a current to flow from the third region of said memory cell.

18. The method of claim 17, further comprising:

reading a state of said memory cell via the current that flows from said third region at the surface.

19. The method of claim 17, wherein the current has an amplitude that is different when said memory cell is in a first data state than when said memory cell is in a second data state.

20. The method of claim 17, further comprising:

writing a first state of said memory cell by injecting a charge to said floating body region via said current that flows from said third region.

21. The method of claim 17, wherein the memory cell further comprises a gate region above the surface and insulated therefrom by an insulating layer.

22. The method of claim 17, wherein the memory cell further comprises a well region of the first conductivity type beneath the buried region.

23. The method of claim 17, further comprising:

applying the electrical signals to said buried region, wherein said electrical signals depend on an operation performed to said memory cells.

24. A method of operating a semiconductor memory array having rows and columns of multi-level memory cells with a surface, the method comprising:

applying electrical signals characterized by at least three amplitude or polarity values to a third region of a memory cell of the semiconductor memory array,

wherein the memory cell comprising;

a floating body region defining at least a portion of the surface, the floating body region having a first conductivity type;

a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type; and

the third region defining at least a further portion of the surface, the third region having the second conductivity type.

25. The method of claim 24, further comprising:

injecting a charge to said floating body region by a current flowing from said third region, wherein the current is caused by the electrical signals applied.

26. The method of claim 24, further comprising:

reading a state of said memory cells from a current flowing from said third region, wherein the current is caused by the electrical signals applied.

27. The method of claim 24, further comprising:

applying the electrical signals to said buried region, where said electrical signals have different amplitudes or polarities, depending on an operation performed to said multi-level memory cells.

28. The method of claim 24, wherein the memory cell further comprises a gate region above the surface and insulated therefrom by an insulating layer.

29. The method of claim 24, wherein the memory cell further comprises a well region beneath the buried region, the well region having a first conductivity type.