CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

• US 20120098109A1
• Filed: 12/08/2011
• Published: 04/26/2012
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Dongkyun Ko, Jaesun An, Jung Lee
• Original Assignee: Dongkyun Ko, Jaesun An, Jung Lee
• Inventors: Ko, Dongkyun, Lee, Jung, An, Jaesun
• Granted Patent: US 8,592,958 B2
• Time in Patent Office: Days
• US Class Current: 257/659
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2203/0415 : Small preforms other than balls, e.g. discs, cylinders or pillars
• CPC Class Codes: H05K 3/0032 : of organic insulating material
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Claims

1. A chip package, comprising:

a substrate;

at least one chip disposed on the substrate and electrically connected to the substrate;

a molding compound disposed over the substrate;

an electromagnetic interference (EMI) shield including a first portion disposed over the molding compound; and

a plurality of conductive connectors spaced from one another and circumscribing a lateral periphery of the molding compound, a lateral surface of at least one of the plurality of conductive connectors being concave.

2. The chip package of claim 1, wherein the at least one of the conductive connectors extends between the first portion of the EMI shield and the substrate.

3. The chip package of claim 2, wherein the conductive connectors provide a ground path between the first portion and the substrate.

4. The chip package of claim 1, wherein the conductive connectors provide partial EMI shielding.

5. The chip package of claim 1, wherein at least one of the plurality of conductive connectors is semi-cylindrical.

6. The chip package of claim 1, wherein the EMI shield comprises a second portion disposed over a lateral surface of the molding compound.

7. The chip package of claim 6, wherein the second portion is coupled to the lateral surface of at least one of the conductive connectors.

8. A semiconductor package comprising:

a substrate;

a chip electrically connected to the substrate;

a package body encapsulating the chip;

an EMI shield including a first portion disposed on an exterior upper surface of the package body; and

a plurality of conductive vias circumscribing the chip, at least one of the plurality of conductive vias having a lateral surface that is concave.

9. The semiconductor package of claim 8, wherein the conductive vias are disposed about a lateral periphery of the package body.

10. The semiconductor package of claim 8, wherein the at least one of the conductive vias extends between the first portion of the EMI shield and the substrate.

11. The semiconductor package of claim 10, wherein the at least one of the conductive connectors provides a ground path between the first portion and the substrate.

12. The semiconductor package of claim 8, wherein the conductive vias provide partial EMI shielding.

13. The semiconductor package of claim 8, wherein the at least one of the plurality of conductive vias is semi-cylindrical.

14. The semiconductor package of claim 8, wherein the EMI shield comprises a second portion disposed over a lateral surface of the molding compound and the second portion is coupled to the lateral surface of at least one of the conductive connectors.

15. The semiconductor package of claim 8, wherein the plurality of conductive vias are oriented at a taper angle with respect to the substrate, and the taper angle is between 60°

-90°

.

16. A method of making a plurality of chip packages, the method comprising:

with a substrate matrix having a plurality of substrate units, electrically connecting at least one chip to each substrate unit;

forming a molding compound over the matrix substrate to encapsulate the chips;

performing a marking process to form a plurality of vias through the molding compound by removing portions of the molding compound until an upper surface of each substrate unit is exposed;

forming a shielding layer over the molding compound to cover the molding compound, and simultaneously forming a plurality of connectors within the vias and covering the exposed upper surface of each substrate unit; and

performing a singulation process to separate the plurality of substrate units and form the plurality of chip packages.

17. The method of claim 16, wherein the connectors are formed as studs filling up the vias.

18. The method of claim 17, wherein the studs are arranged on sawing lines of the matrix substrate and on boundary lines of each substrate unit, and the singulation process cuts through the studs and the matrix substrate.

19. The method of claim 17, wherein the studs are disposed between boundary lines of each substrate unit and the chip, and the singulation process cuts through the matrix substrate but not the studs.

20. The method of claim 16, wherein the connectors are formed by partially filling the vias as plated via structures.