Structures for Preventing Cross-talk Between Through-Silicon Vias and Integrated Circuits

• US 20120104561A1
• Filed: 01/10/2012
• Published: 05/03/2012
• Est. Priority Date: 11/26/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Chen-Cheng
• Granted Patent: US 8,604,594 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 2223/6688 Mixed frequency adaptations, i.e. for operation at different frequencies
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices

Abstract

A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.

Claims

1. A semiconductor chip comprising:

one or more through vias (TVs);

a device region; and

a cross-talk prevention ring encircling one of the device region and the one or more TVs, wherein the one or more TVs are isolated from device regions comprising active devices by the cross-talk prevention ring, the cross-talk prevention ring comprising a plurality of conductive lines vertically arranged, adjacent ones of the plurality of conductive lines being electrically coupled.

2. The semiconductor chip of claim 1, further comprising a seal ring encircling the cross-talk prevention ring and the device region.

3. The semiconductor chip of claim 1, further comprising a sacrificial ring between the seal ring and edges of the semiconductor chip.

4. The semiconductor chip of claim 1, wherein the device region is positioned between the cross-talk prevention ring and the seal ring.

5. The semiconductor chip of claim 1, further comprising a seal ring adjacent to edges of the semiconductor chip, wherein the cross-talk prevention ring comprises a seal ring extension and a portion of the seal ring.

6. The semiconductor chip of claim 1, wherein the cross-talk prevention ring comprises a diffusion region in a semiconductor substrate, the diffusion region being electrically coupled to the plurality of conductive lines.

7. The semiconductor chip of claim 1, wherein the cross-talk prevention ring comprises a dielectric region formed in a trench of a semiconductor substrate.

8. The semiconductor chip of claim 1, wherein the cross-talk prevention ring is grounded.

9. A semiconductor chip comprising:

a seal ring extending along a perimeter of the semiconductor chip;

a cross-talk prevention ring encircled by the seal ring, the cross-talk prevention ring comprising at least one conductive line and a ring region in an underlying substrate;

a through via (TV) in a region between the seal ring and the cross-talk prevention ring; and

a device region encircled by the cross-talk prevention ring, wherein the device region comprises active devices.

10. The semiconductor chip of claim 9, wherein the ring region comprises a doped region in the underlying substrate.

11. The semiconductor chip of claim 10, wherein the ring region is electrically coupled to the at least one conductive line.

12. The semiconductor chip of claim 9, wherein the ring region comprises a trench in the underlying substrate filled with a dielectric material.

13. The semiconductor chip of claim 9, wherein the cross-talk prevention ring is grounded.

14. The semiconductor chip of claim 9, wherein the region between the seal ring and the cross-talk prevention ring is substantially free from active devices.

15. A semiconductor chip comprising:

a seal ring;

a plurality of through vias (TVs); and

a cross-talk prevention ring, the cross-talk prevention ring positioned between a first one or more of the plurality of TVs and a second one or more of the plurality of TVs.

16. The semiconductor chip of claim 15, wherein the cross talk prevention ring comprises one or more conductive lines in dielectric layers overlying a semiconductor substrate.

17. The semiconductor chip of claim 15, wherein the cross talk prevention ring comprises a substrate ring formed in a semiconductor substrate.

18. The semiconductor chip of claim 17, wherein the substrate ring comprises a doped portion of the semiconductor substrate.

19. The semiconductor chip of claim 17, wherein the substrate ring comprises a dielectric portion in the semiconductor substrate.

20. The semiconductor chip of claim 17, wherein the substrate ring comprises a conductive ring formed in the semiconductor substrate.