SYSTEM, METHOD AND APPARATUS FOR ERROR CORRECTION IN MULTI-PROCESSOR SYSTEMS
First Claim
1. A method of synchronizing the state of a plurality of computing modules in an electronic system, each computing module having a processor, comprising:
- hashing processor state data for each of the plurality of computing modules;
comparing the processor hashes for the processor state data; and
re-synchronizing the plurality of computing modules based at least on the compared processor hashes.
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Abstract
This disclosure provides apparatus, methods and systems for error correction in multi processor systems. Some implementations include a plurality of computing modules, each computing module including a processor. Each processor may include processing state. In some other implementations, each computing module may also include a memory. Upon receiving a signal to perform a partial re-synchronization, a hash of each processor'"'"'s state data may be performed. In some embodiments, a hash of at least a portion of each computing module'"'"'s memory data may also be performed. The hashes for each processor are then compared to determine majority hashes and possible minority hashes. Upon identifying a minority hash, the computing module that produced the minority hash may receive new processing state data from one of the computing modules that produced a majority hash.
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Citations
34 Claims
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1. A method of synchronizing the state of a plurality of computing modules in an electronic system, each computing module having a processor, comprising:
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hashing processor state data for each of the plurality of computing modules; comparing the processor hashes for the processor state data; and re-synchronizing the plurality of computing modules based at least on the compared processor hashes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18)
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17. A fault tolerant computing apparatus, comprising:
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a plurality of computing modules, wherein each computing module comprises a processor having processor state data; a hashing module configured to generate hash values of the processor state data; and a fault tolerant checking unit configured to receive the plurality of hash values and determine if each computing module is synchronized with the other computing modules. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
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29. A fault tolerant computing apparatus, comprising:
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a plurality of computing modules, wherein each computing module comprises a processor having processor state data; means for hashing configured to generate hash values of the processor state data; means for comparing the plurality of hash values; and means for determining if the processor within each computing module is synchronized with the processors of the other computing modules. - View Dependent Claims (30, 31, 32)
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33. A non-transitory, computer readable storage medium having instructions stored thereon that cause a processing circuit to perform a method comprising:
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hashing processor state data for each of a plurality of computing modules; comparing the processor hashes for the processor state data; and re-synchronizing the plurality of computing modules based at least on the compared processor hashes. - View Dependent Claims (34)
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Specification