Translating a User Design in A Configurable IC for Debugging the User Design

• US 20120117525A1
• Filed: 11/07/2011
• Published: 05/10/2012
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Andrew Caldwell, Brad Hutchings, Steve Teig
• Inventors: Hutchings, Brad, Caldwell, Andrew, Teig, Steven
• Granted Patent: US 8,429,579 B2
• Time in Patent Office: Days
• US Class Current: 716/103
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing

Abstract

Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.

Claims

1-23. -23. (canceled)

24. A method of debugging an integrated circuit (IC) design, said method comprising:

receiving, at a computing device, a first IC design and a specification of an examination point for monitoring a particular location in the first IC design;

converting the first IC design into a second IC design for implementation on an IC that comprises a plurality of configurable circuits;

identifying a set of observable locations in the IC according to the second IC design, wherein values at the set of observable locations determine values at the examination point in the first IC design; and

tracking the values at the examination point of the first IC design by monitoring the set of observable locations in the IC.

25. The method of claim 24, wherein the IC comprises a debug network, wherein the set of observable locations is directly accessible by the debug network.

26. The method of claim 24, wherein the IC comprises a debug network, wherein monitoring the set of observable locations in the IC comprises accessing a set of circuit elements in the IC through the debug network.

27. The method of claim 24, wherein the examination point does not correspond to a physical circuit element in the IC.

28. The method of claim 24 further comprising identifying a logic function for determining the values at the examination point of the first IC design from the monitored values at the set of observable locations.

29. The method of claim 28, wherein tracking the values at the examination point comprises using the identified logic function and the monitored values at the set of observable locations to compute values at the examination point.

30. The method of claim 24, wherein tracking the values at the examination point further comprises translating values read from the set of observable locations into the values that the examination point would have had in the first IC design.

31. The method of claim 24, wherein converting the first IC design into the second IC design comprises:

translating the first IC design into a netlist, wherein the netlist comprises a set of circuit elements implementing the first IC design; and

producing the second IC design by eliminating at least one of the circuit elements from the netlist, wherein the eliminated circuit element corresponds to the examination point in the first IC design.

32. A non-transitory machine readable medium storing a program that debugs an integrated circuit (IC) design, said program executable by a processor, the program comprising sets of instructions for:

receiving a first IC design and a specification of an examination point for monitoring a particular location in the first IC design;

converting the first IC design into a second IC design for implementation on an IC that comprises a plurality of configurable circuits;

identifying a set of observable locations in the IC according to the second IC design, wherein values at the set of observable locations determine values at the examination point in the first IC design; and

tracking the values at the examination point of the first IC design by monitoring the set of observable locations in the IC.

33. The non-transitory machine readable medium of claim 32, wherein the IC comprises a debug network, wherein the set of observable locations is directly accessible by the debug network.

34. The non-transitory machine readable medium of claim 32, wherein the IC comprises a debug network, wherein the set of instructions for monitoring the set of observable locations in the IC comprises a set of instructions for accessing a set of circuit elements in the IC through the debug network.

35. The non-transitory machine readable medium of claim 32, wherein the examination point does not correspond to a physical circuit element in the IC.

36. The non-transitory machine readable medium of claim 32 further comprising a set of instructions for identifying a logic function for determining the values at the examination point of the first IC design from the monitored values at the set of observable locations.

37. The non-transitory machine readable medium of claim 36, wherein the set of instructions for tracking the values at the examination point comprises a set of instructions for using the identified logic function and the monitored values at the set of observable locations to compute values at the examination point.

38. The non-transitory machine readable medium of claim 32, wherein the set of instructions for tracking the values at the examination point further comprises a set of instructions for translating values read from the set of observable locations into the value that the examination point would have had in the first IC design.

39. The non-transitory machine readable medium of claim 32, wherein the set of instructions for converting the first IC design into the second IC design comprises sets of instructions for:

translating the first IC design into a netlist, wherein the netlist comprises a set of circuit elements implementing the first IC design; and

producing the second IC design by eliminating at least one of the circuit elements from the netlist, wherein the eliminated circuit element corresponds to the examination point in the first IC design.

40. A method of debugging an integrated circuit (IC) design, the IC design comprising a specification of an examination point for monitoring a particular location in the IC design, the IC design optimized for implementation on an IC that comprises a plurality of configurable circuits, the method comprising:

identifying a set of observable locations in the IC, wherein values at the set of observable locations determine values at the examination point in the IC design; and

tracking the values at the examination point of the IC design by monitoring the set of observable locations in the IC.

41. The method of claim 40, wherein the IC comprises a debug network, wherein the set of observable locations is directly accessible by the debug network.

42. The method of claim 40, wherein the examination point does not correspond to a physical circuit element in the IC.

43. The method of claim 40 further comprising identifying a logic function for determining the values at the examination point of the IC design from the monitored values at the set of observable locations, wherein tracking the values at the examination point comprises using the identified logic function and the monitored values at the set of observable locations to compute values at the examination point.