Safe Arming System and Method

• US 20120118190A1
• Filed: 09/02/2010
• Published: 05/17/2012
• Est. Priority Date: 09/04/2009
• Status: Active Grant

• Current Assignee: Vertex Aerospace, LLC
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Fisher, Delmer D.
• Granted Patent: US 8,528,478 B2
• Time in Patent Office: Days
• US Class Current: 102/215
• CPC Class Codes: F42C 15/44 Arrangements for disarming, or for rendering harmless, fuzes after arming, e.g. after launch

Abstract

According to certain embodiments, an arming system includes a first logic device and a second logic device that are both coupled to a detonation circuit operable to initiate a detonation device. The second logic device is operable to receive one or more first signals generated by the first logic device, determine a first fault condition of the first logic device according to the received one or more first signals, and disable the detonation circuit according to the determined first fault condition.

Claims

1. An arming system comprising:

a first logic device coupled to a detonation circuit that is operable to initiate a detonation device; and

a second logic device coupled to the detonation circuit and the first logic device, the second logic device operable to;

receive one or more first signals generated by the first logic device;

determine a first fault condition of the first logic device according to the received one or more first signals; and

disable the detonation circuit according to the determined first fault condition.

2. The arming system of claim 1, wherein the first logic device is operable to:

receive one or more second signals generated by the second logic device;

determine a second fault condition of the second logic device according to the received one or more second signals; and

disable the detonation circuit according to the determined second fault condition.

3. The arming system of claim 1, wherein the first logic device comprises a memory coupled to a processor that executes instructions stored in the memory, and the second logic device comprises a programmable logic device.

4. The arming system of claim 1, wherein the first logic device and the second logic device each comprise a memory coupled to a processor that executes instructions stored in the memory.

5. The arming system of claim 1, wherein the first logic device and the second logic device each comprises a programmable logic device.

6. The arming system of claim 1, wherein the second logic device is operable to determine the fault condition based on not receiving the one or more first signals within a specified period of time.

7. The arming system of claim 1, further comprising a receiver circuit coupled to the first logic device and the second logic device, the first logic device and the second logic device operable to inhibit the detonation circuit according to a wireless signal received from the receiver circuit.

8. The arming system of claim 1, further comprising at least two arming pin switches coupled to the first logic device and the second logic device, the first logic device and the second logic device operable to inhibit the detonation circuit based on a failure of either of the at least two arming pin switches.

9. The arming system of claim 1, wherein the first logic device comprises a first clock and the second logic device comprises a second clock that operates independently of the first clock.

10. An arming method comprising:

receiving, by a second logic device, one or more first signals generated by a first logic device operable to initiate a detonation device;

determining, by the second logic device, a first fault condition of the first logic device according to the received one or more first signals; and

disabling, by the second logic device, the detonation circuit according to the determined first fault condition.

11. The arming method of claim 10, further comprising:

receiving, by the first logic device, one or more second signals generated by the second logic device;

determining, by the first logic device, a second fault condition of the second logic device according to the received one or more second signals; and

disabling, by the first logic device, the detonation circuit according to the determined second fault condition.

12. The arming method of claim 10, wherein the first logic device comprises a memory coupled to a processor that executes instructions stored in the memory, and the second logic device comprises a programmable logic device.

13. The arming method of claim 10, wherein the first logic device and the second logic device each comprise a memory coupled to a processor that executes instructions stored in the memory.

14. The arming method of claim 10, wherein the first logic device and the second logic device each comprises a programmable logic device.

15. The arming method of claim 10, wherein determining the first fault condition by the second logic device comprises determining the first fault condition based on not receiving the one or more first signals with a specified period of time.

16. The arming method of claim 10, further comprising

inhibiting, by the first logic device and the second logic device, the detonation circuit according to a wireless signal received from a receiver circuit.

17. The arming method of claim 10, further comprising inhibiting, by the first logic device and the second logic device, the detonation circuit based on a failure of either of at least two arming pin switches.

18. The arming method of claim 10, further comprising:

clocking the first logic device using a first clock; and

clocking the second logic device using a second clock that operates independently of the first clock.

19. An arming system comprising:

a detonation circuit configured to initiate a detonation device;

a first logic device coupled to the detonation circuit and operable to initiate the detonation device; and

a second logic device coupled to the detonation circuit and the first logic device, the second logic device operable to;

receive one or more first signals generated by the first logic device;

determine a first fault condition of the first logic device according to the received one or more first signals; and

disable the detonation circuit according to the determined first fault condition.

20. The arming system of claim 19, wherein the first logic device is operable to:

receive one or more second signals generated by the second logic device;

determine a second fault condition of the second logic device according to the received one or more second signals; and

disable the detonation circuit according to the determined second fault condition.

21. The arming system of claim 19, wherein the first logic device comprises a memory coupled to a processor that executes instructions stored in the memory, and the second logic device comprises a programmable logic device.

22. The arming system of claim 19, wherein the first logic device and the second logic device each comprise a memory coupled to a processor that executes instructions stored in the memory.

23. The arming system of claim 19, wherein the first logic device and the second logic device each comprises a programmable logic device.

24. The arming system of claim 19, wherein the second logic device is operable to determine the fault condition based on not receiving the one or more first signals with a specified period of time.

25. The arming system of claim 19, further comprising a receiver circuit coupled to the first logic device and the second logic device, the first logic device and the second logic device operable to inhibit the detonation circuit according to a wireless signal received from the receiver circuit.

26. The arming system of claim 19, further comprising at least two arming pin switches coupled to the first logic device and the second logic device, the first logic device and the second logic device operable to inhibit the detonation circuit based on a failure of either of the at least two arming pin switches.

27. The arming system of claim 19, wherein the first logic device comprises a first clock and the second logic device comprises a second clock that operates independently of the first clock.