MEMORY BLOCK MANAGEMENT

• US 20120124304A1
• Filed: 01/10/2012
• Published: 05/17/2012
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Chen, Alan, Nemazie, Siamack
• Granted Patent: US 8,312,245 B2
• Time in Patent Office: Days
• US Class Current: 711/159
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

One or more embodiments comprise control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks. The control circuitry can be configured to: determine defective physical blocks among the number of planes; responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and responsive to one or more of the physical blocks at a particular block position being determined to be defective, assign non-defective physical blocks at the particular block position to a super block and assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block.

Claims

1. A controller, comprising:

control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks, the control circuitry configured to;

determine defective physical blocks among the number of planes;

responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and

responsive to one or more of the physical blocks at a particular block position being determined to be defective;

assign non-defective physical blocks at the particular block position to a super block; and

assign a replacement physical block to the super block for the respective defective physical blocks at the particular block position, the replacement physical block selected from a number of physical blocks within a respective plane that includes a respective defective physical block.

2. The controller of claim 1, wherein each of the one or more memory devices comprises at least two planes, and wherein each super block includes a physical block from each of the at least two planes.

3. The controller of claim 1, wherein an amount of physical blocks from which the replacement physical block is selected is determined based, at least partially, on an uppermost expected number of defective blocks per plane.

4. The controller of claim 1, wherein the control circuitry is configured to treat an otherwise non-defective physical block as a defective block for each physical block within a particular same array as, and at the same particular block position as, a physical block determined to be defective.

5. A controller, comprising:

control circuitry coupled to one or more memory devices having a number of planes of physical blocks organized into super blocks, the control circuitry configured to;

selectively assign at least some of the physical blocks to one of a super block of a first type and a super block of a second type;

wherein the first type of super block includes only physical blocks at a same block position across the number of planes; and

wherein the second type of super block includes;

physical blocks, at a particular block position across the number of planes, determined to be non-defective and;

at least one physical block that replaces a physical block determined to be defective and located at the particular block position.

6. The controller of claim 5, wherein the control circuitry is configured to access a table that includes:

a number of entries each having mapping information corresponding to a respective super block of the first type; and

a number of entries each having an indication of a different table having mapping information corresponding to a respective super block of the second type.

7. The controller of claim 5, wherein:

each of the one or more memory devices comprises at least one memory array, the at least one memory array organized into at least two planes; and

each super block includes a physical block from each of the at least two planes from at least two memory arrays.

8. A controller, comprising:

control circuitry coupled to one or more memory devices having physical blocks organized into super blocks, with each super block including a physical block from each of at least two planes, and wherein the control circuitry is configured to;

assign at least some of the physical blocks to one of a super block of a first type and a super block of a second type, each type of super block including no more than one physical block from a particular plane, wherein the first type of super block includes only physical blocks at a particular block position across the at least two planes; and

determine if a physical block from the at least two planes is defective; and

assign, to a super block of the second type, a physical block at the block position of the physical block determined to be defective, and which has been determined to be non-defective.

9. The controller of claim 8, wherein the control circuitry is configured to prevent a block, at the block position of, and in a same array as a block determined to be defective, that has been determined to be non-defective, from being assigned to a super block of the second type.

10. The controller of claim 8, wherein one or more super blocks of the second type includes at least two blocks at a same block position.

11. The controller of claim 8, wherein one or more super blocks of the second type includes at least three blocks at a same block position.

12. The controller of claim 8, wherein the first and second type of super blocks each include a same number of physical blocks.

13. A system comprising:

a memory unit comprising a number of memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes; and

a controller coupled to the memory unit and configured to control;

determining defective physical blocks within the memory unit; and

assigning a physical block from each of the at least two planes to respective super blocks, wherein each of the super blocks includes;

physical blocks determined to be non-defective and having a same block position corresponding thereto; and

a replacement block for those physical blocks having the same block position and determined to be defective.

the replacement physical block selected from physical blocks within a same plane as the physical block determined to be defective.

14. The system of claim 13, wherein the replacement block is selected from physical blocks within a same plane as that of the defective physical block being replaced.

15. The system of claim 13, wherein the controller is configured to assign an amount of physical blocks within each plane to be used to replace physical blocks within the plane determined to be defective.

16. A system comprising:

a memory unit comprising a number of memory devices and having a number of different planes of physical blocks; and

a controller coupled to the memory unit and configured to control;

assigning physical blocks to a super block of a first type associated with the memory unit, with each super block of the first type including a physical block from each of the number of different planes;

assigning physical blocks to a super block of a second type associated with the memory unit;

wherein each super block of the first type includes only physical blocks at a particular block position across the number of different planes; and

wherein each super block of the second type includes;

a physical block at a particular block position across the number of different planes; and

a replacement block at a different block position, the replacement block replacing a physical block at the particular block position and determined to be defective.

17. The system of claim 16, wherein the controller is configured to prevent physical blocks at a same block position and in a same array as a block determined to be defective from being assigned to a super block of the second type.

18. The system of claim 16, including a table comprising:

a number of entries each having mapping information corresponding to a respective super block of the first type; and

a number of entries each having an indication of a different table having mapping information corresponding to a respective super block of the second type.

19. The method of claim 18, wherein the controller is configured to control searching the different table to determine a physical super block address of a particular super block of the second type based on a particular logical super block address.

20. A system, comprising:

a memory unit comprising a number of memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes; and

a controller coupled to the memory unit and configured to;

determine defective physical blocks within the planes, the defective physical blocks including original defective blocks as well as grown defective blocks;

responsive to none of the physical blocks at a particular block position being determined to be defective, assign the physical blocks at the particular block position to a super block; and

responsive to one or more of the physical blocks at a particular block position being determined to be defective;

assign non-defective physical blocks at the particular block to a super block; and

assign a replacement physical block to the super block for each of the one or more defective physical blocks at the particular block position;

wherein the replacement physical block is selected from an assigned group of physical blocks within a respective one of the planes that includes the defective physical block.

21. The memory controller of claim 20, wherein the controller is configured to, responsive to one or more of the physical blocks currently assigned to a particular super block becoming a grown defective block, assign a replacement block for the grown defective block from the assigned group of physical blocks within the respective one of the planes.