ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS

• US 20120124333A1
• Filed: 01/19/2012
• Published: 05/17/2012
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Granted Patent: US 8,543,795 B2
• Time in Patent Office: Days
• US Class Current: 712/30
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1-74. -74. (canceled)

75. An adaptive computing engine, comprising:

a configurable logic unit comprising a first plurality of heterogeneous computational elements and a first interconnection network coupling the plurality of heterogeneous computational elements to each other, the first plurality of heterogeneous computational elements comprising a first type of heterogeneous computational element for performing a first operation and a second type of heterogeneous computational element for performing a second, different operation;

a configurable processing unit comprising a second plurality of heterogeneous computational elements at least two of which perform an arithmetic operation dedicated to digital signal processing and each having components in a fixed architecture with fixed connections between the components, the configurable processing unit configurable to perform a digital signal processing function; and

wherein the configurable logic unit is configurable to perform a function via changing interconnections of the first interconnection network between the first plurality of heterogeneous computational elements.

76. The adaptive computing engine of claim 75, wherein the first and second types of heterogeneous computational elements comprise different ones of a group of an adder, a register, and a function generator having data inputs and a control input to select a specific function.

77. The adaptive computing engine of claim 75, further comprising a second interconnection network coupled to the configurable logic unit and the configurable processing unit, the second interconnection network for sending configuration information to the first interconnection network.

78. The adaptive computing engine of claim 75, wherein the first interconnection network includes multiplexers coupled to the computational elements, the multiplexers routing data between the computational elements.

79. The adaptive computing engine of claim 77, wherein the first interconnection network has denser interconnections than the interconnections of the second interconnection network.

80. The adaptive computing engine of claim 78 wherein the first interconnection network routes control signals to control the multiplexers to switch data to the computational elements.

81. The adaptive computing engine of claim 78, wherein the configurable logic unit further includes a third type of computational element for performing a third operation selected from the group of an adder, a register, and a function generator having data inputs and a control input to select a specific function.

82. The adaptive computing engine of claim 75, wherein the function is a logic function, arithmetic function or a register function.

83. The adaptive computing engine of claim 75, wherein the first interconnection network provides second configuration information to configure the configurable logic unit to perform a second function.

84. The adaptive computing engine of claim 75, wherein at least two of the heterogeneous computational elements of the configurable processing unit perform a function selected from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

85. The adaptive computing engine of claim 84, wherein the configurable processing unit includes a third interconnection network coupling the computational elements to each other, the configuration information allowing the third interconnection network to connect the computational elements to allow the configurable processing unit to perform a second digital signal processing function.

86. The adaptive computing engine of claim 85, wherein the second function is one of a fixed point arithmetic function, floating point arithmetic functions, filters, or transformation functions.

87. The adaptive computing engine of claim 75, wherein the function performed by the configurable logic unit is bit level manipulation and the digital signal processing function is bit or word level manipulation.

88. The adaptive computing engine of claim 76, wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder.

89. The adaptive computing engine of claim 88, wherein the function includes bit level manipulation;

and wherein the digital signal processing function includes bit or word level manipulation.

90. An adaptive computing engine, comprising:

a configurable processing unit comprising a first interconnection network, and a plurality of heterogeneous computational elements, at least two of which perform an arithmetic function, and, the plurality of heterogeneous computational elements comprising a multiplier computational element and an adder computational element, and each having components in a fixed architecture with fixed connections between the components, the first interconnection network coupled to the heterogeneous computational elements; and

wherein the configurable processing unit is configurable to perform a signal processing function via switching interconnections of the first interconnection network between the plurality of heterogeneous computational elements.

91. The adaptive computing engine of claim 90, further comprising:

a configurable logic unit including a plurality of computational elements; and

a second interconnection network coupled to the configurable logic unit and the configurable processing unit, the second interconnection network for sending configuration information to the configurable processing unit.

92. The adaptive computing engine of claim 91, wherein the plurality of computational elements of the configurable logic unit comprises an adder, a register, or a function generator having data inputs and a control input to select a specific function.

93. The adaptive computing engine of claim 90, wherein the first interconnection network includes multiplexers coupled to the multiplier and adder computational elements, the multiplexers routing data between the computational elements.

94. The adaptive computing engine of claim 91, wherein the first interconnection network switches the interconnections between the heterogeneous computational elements to configure the configurable processing unit to perform a second function.

95. The adaptive computing engine of claim 94, wherein the second function is one of a fixed point arithmetic function, floating point arithmetic functions, filters, or transformation functions.

96. The adaptive computing engine of claim 91, wherein the configurable logic unit is configured via the interconnection network to perform a basic logic function.

97. The adaptive computing engine of claim 91, wherein the configurable logic unit is configured via the interconnection network to perform a bit level function.

98. The adaptive computing engine of claim 90, wherein at least two of the heterogeneous computational elements of the configurable processing unit each perform a function from the group of subtraction, accumulation, summation and dynamic shift.

99. The adaptive computing engine of claim 90, wherein the configurable processing unit is configured to perform the signal processing function by bypassing a first type of heterogeneous computational element and connecting a second type of heterogeneous computational element via the first interconnection network and is configured to perform a different function by connecting the first and second types of heterogeneous computational elements via the first interconnection network.

100. An adaptive computing engine, comprising:

a configurable processing unit comprising a first interconnection network, a first type of computational element and a second type of computational element, the first and second types of computational elements coupled to the first interconnection network, the first and second type of computational elements each for performing an arithmetic function and each having components in a fixed architecture with fixed connections between the components; and

wherein the configurable processing unit may be configured to perform a first function by bypassing at least one of the first type of computational elements and connecting at least one of the second type of computational elements via the first interconnection network and may be configured to perform a different function by connecting at least one of each of the first and second types of computational elements via the first interconnection network.

101. The adaptive computing engine of claim 100 further comprising a configurable logic unit including a plurality of computational elements.

102. The adaptive computing engine of claim 101, further comprising a second interconnection network coupled to the configurable logic unit and the configurable processing unit, the interconnection network for sending configuration information to the configurable processing unit to configure the configurable processing unit to perform the first function or a different function.

103. The adaptive computing engine of claim 102, wherein at least two of the computational elements of the configurable logic unit are one of a group of an adder, a register, and a function generator having data inputs and a control input to select a specific function.

104. The adaptive computing engine claim 102, wherein the configurable logic unit further includes a third interconnection network coupled to the first and second types of computational elements.

105. The adaptive computing engine of claim 100, wherein the first unit interconnection network includes multiplexers coupled to the two types of computational elements, the multiplexers routing data between the computational elements.

106. The adaptive computing engine of claim 100, wherein at least two of the computational elements of the configurable processing unit each perform a function from the group of multiplication, addition, subtraction, accumulation, summation and dynamic shift.

107. The adaptive computing engine of claim 100, wherein the first and different functions include a bit or word level manipulation.

108. The adaptive computing engine of claim 101, wherein the plurality of computational elements of the configurable logic unit is configurable to perform a logic function including bit level manipulation;

and wherein the functions of the configurable processing unit includes bit or word level manipulation.

109. The adaptive computing engine of claim 101, wherein the plurality of computational elements of the configurable logic unit is configurable to perform a logic function including a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the functions of the digital signal processing unit include a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

110. The adaptive computing engine of claim 109, wherein the logic function includes bit level manipulation;

and wherein the signal processing function includes word or bit level manipulation.

111. A configurable computational unit comprising:

a first plurality of adder computational elements, each having components with fixed connections therebetween;

a second plurality of multiplier computational elements, each having components with fixed connections therebetween;

an arithmetic logical computational element having components with fixed connections therebetween; and

an interconnection network coupling the plurality of adder computational elements, the plurality of multiplier computational elements and the arithmetic logical computational element to each other, wherein the configurable computational unit is configurable to perform a complex function via switching interconnections of the interconnection network among the plurality of adder computational elements, the plurality of multiplier computational elements and the arithmetic logical computational element.

112. The configurable computational unit of claim 111, wherein the configurable computational unit is configured to perform another complex function by bypassing one of the plurality of adder computational elements, the plurality of multiplier computational elements or the arithmetic logical computational element.

113. The configurable computational unit of claim 111 further comprising another type of computational element of a group of a register or a function generator having data inputs and a control input to select a specific function.

114. The configurable computational unit of claim 111, wherein the interconnection network includes multiplexers coupled to the plurality of adder computational elements, the plurality of multiplier computational elements and the arithmetic logical computational element.

115. The configurable computational unit of claim 111 wherein the interconnection network routes data between the plurality of adder computational elements, the plurality of multiplier computational elements and the arithmetic logical computational element.

116. The configurable computational unit of claim 111, wherein the complex function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

117. The configurable computational unit of claim 111, wherein the complex function is a signal processing function.