SEMICONDUCTOR STRUCTURES INCLUDING POLYMER MATERIAL PERMEATED WITH METAL OXIDE

• US 20120133017A1
• Filed: 12/22/2011
• Published: 05/31/2012
• Est. Priority Date: 10/28/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Millward, Dan B., Quick, Timothy A., Greeley, J. Neil
• Granted Patent: US 8,669,645 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: C08L 2666/02 Organic macromolecular compounds, natural resins, waxes or and bituminous materials
• CPC Class Codes: C08L 53/00 Compositions of block copolymers containing at least one sequence of a polymer obtained by reactions only involving carbon-to-carbon unsaturated bonds; Compositions of derivatives of such polymers
• CPC Class Codes: C08L 53/005 Modified block copolymers
• CPC Class Codes: C09D 153/00 Coating compositions based on block copolymers containing at least one sequence of a polymer obtained by reactions only involving carbon-to-carbon unsaturated bonds; Coating compositions based on derivatives of such polymers
• CPC Class Codes: C09D 153/005 Modified block copolymers
• CPC Class Codes: G03F 7/0002 Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
• CPC Class Codes: H01L 21/02323 introduction of oxygen
• CPC Class Codes: H01L 21/0271 comprising organic layers
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing
• CPC Class Codes: Y10S 977/888 Shaping or removal of materials, e.g. etching
• CPC Class Codes: Y10S 977/89 Deposition of materials, e.g. coating, cvd, or ald

Abstract

Methods of forming metal oxide structures and methods of forming metal oxide patterns on a substrate using a block copolymer system formulated for self-assembly. A block copolymer at least within a trench in the substrate and including at least one soluble block and at least one insoluble block may be annealed to form a self-assembled pattern including a plurality of repeating units of the at least one soluble block laterally aligned with the trench and positioned within a matrix of the at least one insoluble block. The self-assembled pattern may be exposed to a metal oxide precursor that impregnates the at least one soluble block. The metal oxide precursor may be oxidized to form a metal oxide. The self-assembled pattern may be removed to form a pattern of metal oxide lines on the substrate surface. Semiconductor device structures are also described.

Claims

1. A semiconductor device structure comprising:

at least one trench in an insulative material overlying a substrate; and

a plurality of structural domains within the at least one trench, each structural domain of the plurality of structural domains substantially equally laterally spaced from at least one other structural domain of the plurality of structural domains and comprising at least one polymer block permeated with a metal oxide.

2. The semiconductor device structure of claim 1, wherein each structural domain of the plurality of structural domains comprises polyvinylpyridine and the metal oxide.

3. The semiconductor device structure of claim 1, wherein each structural domain of the plurality of structural domains is positioned substantially parallel to sidewalls of the at least one trench.

4. The semiconductor device structure of claim 1, wherein the plurality of structural domains comprises from about two structural domains to about fifty structural domains.

5. The semiconductor device structure of claim 1, wherein the plurality of structural domains comprises at least one of a plurality of lamellas and a plurality of cylinders.

6. The semiconductor device structure of claim 1, wherein the plurality of structural domains comprises a plurality of cylinders, each cylinder of the plurality of cylinders having a diameter with a range of from about 5 nm to about 50 nm.

7. The semiconductor device structure of claim 1, wherein each structural domain of the plurality of structural domains has a length substantially equal to a length of the at least one trench.

8. The semiconductor device structure of claim 1, wherein the at least one polymer block is substantially hydrophilic.

9. The semiconductor device structure of claim 1, wherein the at least one polymer block comprises at least one of polyvinylpyridine, hydroxypropyl methylcellulose, polyethylene glycol, poly(ethylene oxide)-co-poly(propylene oxide), poly(ethylene oxide), poly(vinyl alcohol), poly(ethylene-co-vinyl alcohol), poly(acrylic acid), poly(ethyloxazoline), a poly(alkylacrylate), poly(acrylamide), a poly(Nalkylacrylamide), a poly(N,N-dialkylacrylamide), poly(propylene glycol), poly(propylene oxide), partiallyhydrolyzed poly(vinyl alcohol), fully hydrolyzed poly(vinyl alcohol), dextran, and copolymers thereof.

10. The semiconductor device structure of claim 1, wherein the metal oxide comprises at least one of titanium dioxide and silicon dioxide.

11. The semiconductor device structure of claim 1, wherein the at least one trench has a depth within a range of from about 15 nm to about 50 nm.

12. The semiconductor device structure of claim 1, further comprising:

a dielectric material over and in contact with the substrate; and

a semiconductive material between the dielectric material and the insulative material.

13. A semiconductor device structure comprising:

a plurality of structural domains within at least one trench in an insulative material overlying a substrate, each structural domain of the plurality of structural domains comprising;

a polymer material; and

a metal oxide within the polymer material; and

a matrix at least partially surrounding each structural domain of the plurality of structural domains.

14. The semiconductor device structure of claim 13, wherein the polymer material comprises a hydrophilic polymer.

15. The semiconductor device structure of claim 13, further comprising a conformal film of dielectric material on surfaces of the at least one trench.

16. The semiconductor device structure of claim 13, wherein the matrix comprises a hydrophobic polymer.

17. The semiconductor device structure of claim 13, wherein the matrix comprises at least one of polystyrene, polyethylene, polypropylene, polychloroprene, a polyvinyl ether, poly(vinyl acetate), poly(vinyl chloride), a polysiloxane, apolyurethane, a polyacrylate, a polyacrylamide, and copolymers thereof.

18. A semiconductor device structure comprising:

an insulative material over a substrate;

a plurality of polymer blocks within at least one trench in the insulative material; and

a metal oxide within at least one polymer block of the plurality of polymer blocks.

19. The semiconductor device structure of claim 18, wherein the plurality of polymer blocks comprises a self-assembled block copolymer material comprising at least one of polystyrene-block-polyvinylpyridine, polystyrene-block-polymethylmethacrylate, polyethyleneoxide-block-polyisoprene, polyethyleneoxide-block-polybutadiene, polyethyleneoxide-block-polystyrene, polyethyleneoxide-block-polymethylmethacrylate, polyethyleneoxide-block-polyethylethylene, polystyrene-block-polyisoprene, polystyrene-block-polybutadiene, polystyrene-block-polyferrocenyldimethylsilane, polybutadiene-block-polyvinylpyridine, and polyisoprene-block-polymethylmethacrylate.

20. The semiconductor device structure of claim 18, wherein the plurality of polymer blocks comprises a plurality of substantially equally laterally spaced polymer structures.