INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VERTICAL INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF

• US 20120146229A1
• Filed: 12/10/2010
• Published: 06/14/2012
• Est. Priority Date: 12/10/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Cho, SungWon, Bae, JoHyun, Choi, DaeSik, Moon, DongSoo
• Granted Patent: US 9,093,392 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB printed circuits H05K1/00
• CPC Class Codes: H01L 2225/1082 : for improving alignment between containers, e.g. interlocking features
• CPC Class Codes: H01L 23/13 : characterised by the shape
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window; mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side; attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window; forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

attaching a lower internal connector to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window;

forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and

forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

2. The method as claimed in claim 1 wherein forming the upper insulation includes forming the upper insulation having an upper insulation cavity exposing the base inactive side.

3. The method as claimed in claim 1 further comprising forming a central through-insulation connector through the upper insulation and over the base inactive side.

4. The method as claimed in claim 1 wherein forming the upper insulation includes forming the upper insulation with the base inactive side fully exposed from the upper insulation.

5. The method as claimed in claim 1 further comprising attaching a stack structure to the peripheral connector top side.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

mounting a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

attaching a lower internal connector to the base active side and the package substrate bottom side;

forming a lower insulation over the lower internal connector and the base integrated circuit;

forming an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and

forming a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

7. The method as claimed in claim 6 further comprising connecting a stack integrated circuit to the base integrated circuit.

8. The method as claimed in claim 6 further comprising mounting a top structure having a top component over an upper insulation cavity of the upper insulation.

9. The method as claimed in claim 6 further comprising mounting a top structure having a top substrate bottom side over the peripheral through-insulation connector, a top component active side connected to the top substrate bottom side, and a top component inactive side facing the base integrated circuit.

10. The method as claimed in claim 6 further comprising mounting a top structure having a top substrate bottom side over the peripheral through-insulation connector, a top component inactive side attached to the top substrate bottom side, and a top component active side facing the base integrated circuit.

11. An integrated circuit packaging system comprising:

a package substrate having a package substrate bottom side, a package substrate top side, and a package substrate window;

a base integrated circuit over the package substrate, the base integrated circuit having a base inactive side and a base active side facing the package substrate top side;

a lower internal connector attached to the base active side and the package substrate bottom side, the lower internal connector through the package substrate window;

an upper insulation conformal to the base integrated circuit and the package substrate top side, the upper insulation having an upper insulation top side; and

a peripheral through-insulation connector through the upper insulation, the peripheral through-insulation connector having a peripheral connector bottom side directly on the package substrate top side and a peripheral connector top side coplanar with the upper insulation top side.

12. The system as claimed in claim 11 wherein the upper insulation includes an upper insulation cavity exposing the base inactive side.

13. The system as claimed in claim 11 further comprising a central through-insulation connector through the upper insulation and over the base inactive side.

14. The system as claimed in claim 11 wherein the upper insulation fully exposes the base inactive side.

15. The system as claimed in claim 11 further comprising a stack structure attached to the peripheral connector top side.

16. The system as claimed in claim 11 further comprising a lower insulation over the lower internal connector and the base integrated circuit.

17. The system as claimed in claim 16 further comprising a stack integrated circuit connected to the base integrated circuit.

18. The system as claimed in claim 16 further comprising a top structure having a top component over an upper insulation cavity of the upper insulation.

19. The system as claimed in claim 16 further comprising a top structure having a top substrate bottom side over the peripheral through-insulation connector, a top component active side connected to the top substrate bottom side, and a top component inactive side facing the base integrated circuit.

20. The system as claimed in claim 16 further comprising a top structure having a top substrate bottom side over the peripheral through-insulation connector, a top component inactive side attached to the top substrate bottom side, and a top component active side facing the base integrated circuit.