NITRIDE SEMICONDUCTOR DEVICE

• US 20120153355A1
• Filed: 02/22/2012
• Published: 06/21/2012
• Est. Priority Date: 08/27/2009
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: UMEDA, Hidekazu, Anda, Yoshiharu, Ueda, Tetsuzo, Tanaka, Tsuyoshi, Ueda, Daisuke
• Granted Patent: US 8,872,227 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A nitride semiconductor device includes a semiconductor substrate, and a nitride semiconductor layer formed on the semiconductor substrate. The semiconductor substrate includes a normal region and an interface current block region surrounding the normal region. The nitride semiconductor layer includes an element region and an isolation region surrounding the element region. The element region is formed over the normal region. The interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

Claims

1. A nitride semiconductor device comprising:

a semiconductor substrate; and

a nitride semiconductor layer formed on the semiconductor substrate, wherein

the semiconductor substrate includes a normal region and an interface current block region surrounding the normal region,

the nitride semiconductor layer includes an element region and an isolation region surrounding the element region,

the element region is formed over the normal region, and

the interface current block region contains impurities, and forms a potential barrier against carriers generated at an interface between the nitride semiconductor layer and the semiconductor substrate.

2. The nitride semiconductor device of claim 1, wherein

the interface current block region contains impurities of a same conductivity type as impurities in the normal region, and

the interface current block region has a higher impurity concentration than the normal region.

3. The nitride semiconductor device of claim 1, wherein

the interface current block region contains impurities of a different conductivity type from impurities in the normal region.

4. The nitride semiconductor device of claim 1, wherein

the interface current block region includes

a first region containing impurities of a same conductivity type as impurities in the normal region, and

a second region containing impurities of a different conductivity type from impurities in the normal region, and

the first region has a higher impurity concentration than the normal region.

5. The nitride semiconductor device of claim 4, wherein

the first region is spaced apart from the second region.

6. The nitride semiconductor device of claim 1, wherein

the interface current block region is formed in a portion other than directly under the element region of the semiconductor substrate.

7. The nitride semiconductor device of claim 1, wherein

the interface current block region is exposed on a side surface of the semiconductor substrate.

8. The nitride semiconductor device of claim 1, wherein

the semiconductor substrate includes a depletion layer formation region formed on an inner side of the interface current block region, spaced apart from the interface current block region, and containing impurities of a different conductivity type from impurities in the normal region.

9. The nitride semiconductor device of claim 1, wherein

the semiconductor substrate includes a plurality of depletion layer formation regions, each formed on an inner side of the interface current block region, spaced apart from the interface current block region, and containing impurities of a different conductivity type from impurities in the normal region, and

the plurality of depletion layer formation regions are spaced apart from each other.

10. The nitride semiconductor device of claim 1, wherein

the nitride semiconductor layer is formed on a region of the semiconductor substrate on an inner side of the interface current block region.

11. The nitride semiconductor device of claim 1, wherein

the nitride semiconductor layer includes

a first layer, and

a second layer formed on the first layer and having a greater bandgap than the first layer.

12. The nitride semiconductor device of claim 11, further comprising:

a source electrode;

a drain electrode; and

a gate electrode.

13. The nitride semiconductor device of claim 12, wherein

the nitride semiconductor layer includes a third layer selectively formed on the second layer and containing p-type impurities, and

the gate electrode is formed on the third layer.

14. The nitride semiconductor device of claim 11, further comprising

a cathode electrode and an anode electrode, which are formed on the nitride semiconductor layer.

15. The nitride semiconductor device of claim 1, further comprising:

a source electrode, a drain electrode, and a gate electrode, which are formed on the nitride semiconductor layer; and

a gate insulating film formed between the gate electrode and the nitride semiconductor layer, wherein

the nitride semiconductor layer includes

an n-type first layer, a p-type second layer, and an n-type third layer, which are sequentially formed on the semiconductor substrate, and

a recess penetrating the third layer and the second layer, and reaching the first layer,

the drain electrode is formed in contact with the first layer,

the source electrode is formed in contact with the third layer, and

the gate electrode is formed to fill the recess with the gate insulating film interposed therebetween.

16. The nitride semiconductor device of claim 1, wherein

the interface current block region has an impurity concentration of 1×

10¹⁶ cm<sup>−

3</sup> or more.

17. The nitride semiconductor device of claim 1, further comprising:

a back surface electrode formed on a surface of the semiconductor substrate opposite to the nitride semiconductor layer; and

a through electrode penetrating the nitride semiconductor layer and the semiconductor substrate, and connected to the back surface electrode.

18. The nitride semiconductor device of claim 17, wherein

the through electrode is surrounded by the interface current block region on a top surface of the semiconductor substrate.

19. The nitride semiconductor device of claim 17, wherein

the through electrode is formed to penetrate the interface current block region.

20. The nitride semiconductor device of claim 17, further comprising

a source electrode, a drain electrode, and a gate electrode, which are formed on the nitride semiconductor layer, wherein

the through electrode is connected to any one of the source electrode, the drain electrode, or the gate electrode.