SUSPENDING COLUMN ADDRESSING IN IMAGE SENSORS

• US 20120154655A1
• Filed: 12/20/2010
• Published: 06/21/2012
• Est. Priority Date: 12/20/2010
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Compton, John T., Gerstenberger, Jeffrey S., Mruthyunjaya, Ravi
• Granted Patent: US 8,384,813 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/745 Circuitry for generating timing or clock signals
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers

Abstract

An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. A timing generator outputs a column address sequence that is received by a column decoder that is electrically connected to each output circuit. The timing generator suspends the output of the column address sequence during a sample operation and resumes the output of the column address sequence at the end of the sample operation.

Claims

1. A method for reading out an image from an image sensor including a two-dimensional array of pixels having a plurality of column outputs and an output circuit connected to each column output, wherein each output circuit is configured to operate concurrent sample and read operations, the method comprising:

initiating concurrent sample and read operations in each output circuit;

during a first sample operation, suspending a column address sequence; and

at or after the completion of the first sampling operation, resuming the column address sequence.

2. The method as in claim 1, further comprising:

during a second sample operation, suspending the column address sequence; and

at or after the completion of the second sampling operation, resuming the column address sequence.

3. The method as in claim 1, further comprising selectively storing at least a portion of pixel data output from the output circuits.

4. The method as in claim 2, wherein the column address sequence is suspended during the first sample operation for a predetermined first number of clock periods.

5. The method as in claim 4, wherein the column address sequence is suspended during the second sample operation for a predetermined second number of clock periods.

6. The method as in claim 5, wherein the predetermined first and second numbers of clock periods are the same.

7. The method as in claim 5, wherein the predetermined first and second numbers of clock periods are different.