ADAPTIVE ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUIT

• US 20120154963A1
• Filed: 11/03/2011
• Published: 06/21/2012
• Est. Priority Date: 12/21/2010
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Deval, Philippe, Furrer, Nicolas, Geeter, Bart De
• Granted Patent: US 8,462,473 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

For adaptive electrostatic discharge (ESD) protection, an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, has an external connection pin to be protected from ESD; an external ground connection pin; an adaptive electrostatic discharge (ESD) protection circuit having: an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground; a resistor coupled between a gate of the NMOS transistor and ground; a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground; a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.

Claims

1. An integrated circuit device having an adaptive electrostatic discharge (ESD) protection, comprising:

an external connection pin to be protected from ESD;

an external ground connection pin;

an adaptive electrostatic discharge (ESD) protection circuit comprising;

an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground;

a resistor coupled between a gate of the NMOS transistor and ground;

a first PMOS transistor having a source coupled to a gate of the NMOS transistor and a drain connected to ground;

a first capacitor having a first terminal connected to the external connection pin and a second terminal that is coupled with the gate of the NMOS transistor, wherein the first capacitor within the adaptive ESD protection circuit is the only capacitor connected to the external connection pin.

2. The integrated circuit device according to claim 1, comprising

a second P-metal oxide semiconductor (PMOS) transistor having a drain connected to the second terminal of the first capacitor, a source and bulk connected to the gate of the NMOS transistor and a gate connected to ground, wherein a source and bulk of the first PMOS transistor is connected to the gate of the NMOS transistor and a drain of the first PMOS transistor is connected to ground;

and

a filter coupled between the second terminal of the first capacitor and the gate of the first PMOS transistor.

3. The integrated circuit according to claim 2, wherein the filter comprises a second resistor connected between the second terminal of the first capacitor and a gate of the first PMOS transistor and a second capacitor connected between the source and the gate of the first PMOS transistor.

4. The integrated circuit according to claim 2, wherein the time constant of the filter is about 400 ns.

5. The integrated circuit according to claim 3, wherein the time constant of the filter is about 400 ns.

6. The integrated circuit according to claim 1, further comprising

a data bus interface coupled to the external connection;

a circuit function coupled to the data bus interface.

7. The integrated circuit device of claim 1, wherein the data bus interface is at least one of a data bus receiver and a data bus driver.

8. The integrated circuit device of claim 1, wherein the circuit function is a digital logic function.

9. The integrated circuit device of claim 1, wherein the circuit function is an analog circuit function or a mixed signal circuit function.

10. The integrated circuit device of claim 3, further comprising a third resistor coupled in parallel with said second capacitor.

11. The integrated circuit device of claim 3, further comprising a third PMOS transistor having a drain and gate connected to the gate of the second PMOS transistor, a bulk connected to the bulk of the first PMOS transistor, and a source connected to ground.

12. The integrated circuit device of claim 3, further comprising a third PMOS transistor having a drain and gate connected to the gate of the second PMOS transistor, a bulk and source connected to the bulk and source of the second PMOS transistor.

13. The integrated circuit device of claim 1, wherein a data bus to be connected to the external connection is a Local Interconnect Network (LIN) bus or a Controller Area Network (CAN) bus.

14. The integrated circuit device according to claim 1, comprising

a second P-metal oxide semiconductor (PMOS) transistor having a drain connected to the second terminal of the first capacitor, a source and bulk connected to ground, wherein the source and a bulk of the first PMOS transistor are connected to the gate of the NMOS transistor and a drain of the first PMOS transistor is connected to ground;

and

a filter coupled between the second terminal of the first capacitor and the first PMOS transistor.

15. The integrated circuit device according to claim 14, wherein the gate of the second PMOS transistor is coupled with ground.

16. The integrated circuit device according to claim 15, further comprising a second capacitor coupled between the gate of the NMOS transistor and ground.

17. The integrated circuit device according to claim 14, wherein the gate of the second PMOS transistor is coupled with the gate of the NMOS transistor.

18. The circuit arrangement according to claim 14, wherein the filter comprises a second resistor connected between the second terminal of the first capacitor and a gate of the first PMOS transistor and a second capacitor connected between the source and the gate of the first PMOS transistor.

19. The integrated circuit device of claim 18, further comprising a third resistor coupled in parallel with said second capacitor.

20. The integrated circuit device of claim 18, further comprising a third PMOS transistor having a drain and gate connected to the gate of the first PMOS transistor, a bulk connected to the bulk of the second PMOS transistor, and a source connected to ground.

21. The integrated circuit device of claim 18, further comprising a third PMOS transistor having a drain and gate connected to the gate of the first PMOS transistor, a bulk and source connected to the bulk and source of the first PMOS transistor.

22. The circuit arrangement according to claim 14, wherein the time constant of the filter is about 400 ns.

23. The integrated circuit device according to claim 1, comprising

a second P-metal oxide semiconductor (PMOS) transistor having a drain connected to the second terminal of the first capacitor, a bulk connected to the gate of the NMOS transistor, and a source and gate connected to ground, wherein the source and a bulk of the first PMOS transistor are connected to the gate of the NMOS transistor and the drain of the first PMOS transistor is connected to ground;

a second resistor connected between the second terminal of the first capacitor and a gate of the first PMOS transistor and a second capacitor connected between the source and the gate of the first PMOS transistor, and

a third PMOS transistor having a source and gate connected to the gate of the first PMOS transistor, a drain connected to the ground and a bulk connected to the bulk of the second PMOS transistor.

24. The integrated circuit device according to claim 1, comprising

a second P-metal oxide semiconductor (PMOS) transistor having a drain coupled to the second terminal of the first capacitor, a bulk and source connected to a bulk of the first PMOS transistor, and a gate connected to ground, wherein a gate of the first PMOS transistor is connected to ground.

25. The integrated circuit device according to claim 24, further comprising a second resistor connected between the gate of the NMOS transistor and the drain of the second PMOS transistor.

26. The integrated circuit device according to claim 24, wherein a gate-drain capacitance of the NMOS transistor forms the first capacitor.

27. The integrated circuit device according to claim 26, further comprising a second capacitor connected between the gate of the NMOS transistor and ground.

28. The integrated circuit device according to claim 26, further comprising a second resistor connected between the gate of the NMOS transistor and the first resistor.

29. The integrated circuit device according to claim 1, wherein the resistor is formed by a transistor.

30. The integrated circuit device according to claim 3, wherein the second resistor is formed by a transistor.

31. The integrated circuit device according to claim 18, wherein the second resistor is formed by a transistor.

32. The integrated circuit device according to claim 1, wherein a gate-drain capacitance of the NMOS transistor forms the first capacitor.

33. The integrated circuit device according to claim 32, wherein a bulk and a gate of the first PMOS transistor are connected to ground.

34. The integrated circuit device according to claim 33, wherein the source of the first PMOS transistor is connected with the gate of the NMOS transistor through a second resistor.

35. The integrated circuit device according to claim 1, wherein a bulk and a gate of the first PMOS transistor are connected to ground.

36. The integrated circuit device according to claim 35, wherein the source of the first PMOS transistor is connected with the gate of the NMOS transistor through a second resistor.

37. The integrated circuit device according to claim 36, further comprising a third resistor connected between the second terminal of the first capacitor and the source of the first PMOS transistor.

38. A motor vehicle comprising

a data bus selected from the group consisting of a Local Interconnect Network (LIN) bus and a Controller Area Network (CAN) bus;

an integrated circuit device having an adaptive electrostatic discharge (ESD) protection, the integrated circuit device comprising;

a data bus interface coupled via an external connection pin with said data bus;

a circuit function coupled to the data bus interface;

an external ground connection pin;

an ESD protection N-metal oxide semiconductor (NMOS) transistor having drain connected to the external connection pin and a source and bulk connected to ground;

a resistor coupled between a gate of the NMOS transistor and ground;

a first capacitor having a first terminal connected to the external connection pin;

a first P-metal oxide semiconductor (PMOS) transistor having a drain connected to the second terminal, a source and bulk connected to the gate of the NMOS transistor and a gate connected to ground;

a second PMOS transistor having a source and bulk connected to the gate of the NMOS transistor and a drain connected to ground; and

a filter comprising a second resistor connected between the second terminal of the first capacitor and a gate of the second PMOS transistor and a second capacitor connected between the source and the gate of the second PMOS transistor.