SELF-ALIGNED NAND FLASH SELECT-GATE WORDLINES FOR SPACER DOUBLE PATTERNING

• US 20120156876A1
• Filed: 12/17/2010
• Published: 06/21/2012
• Est. Priority Date: 12/17/2010
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: CHEN, Tung-Sheng, FANG, Shenqing
• Granted Patent: US 8,461,053 B2
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/302 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A method for double patterning is disclosed. In one embodiment the formation a pair of select gate wordlines on either side of a plurality of core wordlines begins by placing a spacer pattern around edges of a photoresist pattern is disclosed. The photoresist pattern is stripped away leaving the spacer pattern. A trim mask is placed over a portion of the spacer pattern. Portions of the spacer pattern are etched away that are not covered by the trim mask. The trim mask is removed, wherein first remaining portions of the spacer pattern define a plurality of core wordlines. A pad mask is placed such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines. Finally at least one pattern transfer layer is etched through using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

Claims

1. A method for double patterning, comprising:

placing a spacer pattern around edges of a photoresist pattern;

stripping away the photoresist pattern leaving the spacer pattern;

placing a trim mask over a portion of the spacer pattern;

etching away portions of the spacer pattern that are not covered by the trim mask;

removing the trim mask, wherein first remaining portions of the spacer pattern define a plurality of core wordlines;

placing a pad mask such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines; and

etching through at least one pattern transfer layer using the pad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicon layer.

2. The method for doubling patterning of claim 1, wherein the at least one pattern transfer layer comprises a silicon oxynitride layer over a hard mask layer.

3. The method for double patterning of claim 1, wherein the spacer pattern is placed around an amorphous carbon pattern transferred from the photoresist pattern.

4. The method for double patterning of claim 1, wherein the spacer pattern is formed from one of an oxide and an amorphous carbon layer.

5. The method for double patterning of claim 1, wherein the pad mask further defines pads.

6. The method for double patterning of claim 1, wherein distances between each of the select gate wordlines and the plurality of core wordlines are equal and set according to a target spacing.

7. The method for double patterning of claim 1, wherein the spacer pattern is 32 nm thick.

8. A method for double patterning, comprising:

placing a spacer pattern around edges of a photoresist pattern;

stripping away the photoresist pattern leaving the spacer pattern;

placing a spin-on-carbon (SOC) layer over the spacer pattern;

etching away the spacer pattern, such that the SOC layer remains to form an SOC pattern;

placing a trim mask over a portion of the SOC pattern;

etching away portions of the SOC pattern not covered by the trim mask;

removing the trim mask, wherein first remaining portions of the SOC pattern define a plurality of core wordlines, wherein second remaining portions of the SOC pattern define a select gate wordline on either side of the plurality of wordlines, wherein the first remaining portions of the SOC pattern also define a dummy wordline between each of the select gate wordlines and the plurality of core wordlines; and

etching through at least one pattern transfer layer using the first and second remaining portions of the SOC pattern to etch the select gate wordlines, the dummy wordlines, and the plurality of core wordlines into a poly silicon layer.

9. The method for doubling patterning of claim 8, wherein the at least one pattern transfer layer comprises a silicon oxynitride layer over a hard mask layer.

10. The method for double patterning of claim 8, wherein the spacer pattern is placed around an amorphous carbon pattern transferred from the photoresist pattern.

11. The method for double patterning of claim 8, wherein the spacer pattern is formed from one of an oxide and an amorphous carbon layer.

12. The method for double patterning of claim 8, wherein distances between each select gate wordline and the dummy wordlines are equal and set according to a target spacing.

13. The method for double patterning of claim 12, wherein a distance between a select gate wordline and a dummy wordline is equal to twice a spacer pattern thickness.

14. The method for double patterning of claim 12, wherein a distance between a select gate wordline and a dummy wordline is no more than twice a spacer pattern thickness.

15. The method for double patterning of claim 8, wherein the spacer pattern is 32 nm thick.

16. A computer readable media comprising computer-executable instructions stored therein, the computer-executable instructions comprising:

instructions to place a spacer pattern around edges of a photoresist pattern;

instructions to strip away the photoresist pattern leaving the spacer pattern;

instructions to place a trim mask over a portion of the spacer pattern;

instructions to etch away portions of the spacer pattern that are not covered by the trim mask;

instructions to remove the trim mask, wherein first remaining portions of the spacer pattern define a plurality of core wordlines;

instructions to place a pad mask such that the pad mask and second remaining portions of the spacer pattern define a select gate wordline on either side of the plurality of core wordlines; and

instructions to etch through at least one pattern transfer layer using the mad mask and the first and second remaining portions of the spacer pattern to etch the select gate wordlines and the plurality of core wordlines into a poly silicone layer.

17. The method for doubling patterning of claim 16, wherein the at least one pattern transfer layer comprises a silicon oxynitride layer over a hard mask layer.

18. The method for double patterning of claim 16, wherein the spacer pattern is placed around an amorphous carbon pattern transferred from the photoresist pattern.

19. The method for double patterning of claim 16, wherein the spacer pattern is formed from one of an oxide and an amorphous carbon layer.

20. The method for double patterning of claim 16, wherein the pad mask further defines pads.

21. The method for double patterning of claim 16, wherein distances between each of the select gate wordlines and the plurality of core wordlines are equal and set according to a target spacing.

22. The method for double patterning of claim 16, wherein the spacer pattern is 32 nm thick.