RETICLE SET MODIFICATION TO PRODUCE MULTI-CORE DIES

• US 20120161328A1
• Filed: 11/17/2011
• Published: 06/28/2012
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Gaskins, Darius D.
• Granted Patent: US 8,637,212 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304

Abstract

A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

Claims

1. A method for producing a reticle set useable to print multi-core dies on a semiconductor wafer, the method comprising:

developing a first reticle set usable to print Q-core dies, wherein the first reticle set defines scribe lines to separate the Q-core dies, wherein the scribe lines collectively define a seal ring to surround each Q-core die, wherein Q is at least 1; and

modifying less than all of the reticles of the first reticle set to produce a second reticle set useable to print P-core dies, wherein said modifying comprises removing at least one defined scribe line of the first reticle set and defining inter-core communication wires to connect at least two adjacent cores that would have been separated by the replaced scribe line, wherein P is at least twice Q;

wherein the inter-core communication wires are configured to enable the at least two connected cores to communicate during operation;

wherein the inter-core communication wires are configured to not connect to physical input/output landing pads of the P-core die, such that a P-core die manufactured in accordance with the modified reticle set will not carry signals through the inter-core communication wires off the P-core die.

2. The method of claim 1, further comprising:

manufacturing a semiconductor wafer of multi-core dies using the second reticle set.

3. The method of claim 2, wherein said manufacturing the semiconductor wafer of multi-core dies using the second reticle set comprises:

printing the multi-core dies on the semiconductor wafer using the second reticle set; and

cutting the multi-core dies on the semiconductor wafer along the remaining scribe lines.

4. The method of claim 1, wherein Q is 1 and P is 2.

5. The method of claim 1, wherein Q is 2 and P is 4.

6. The method of claim 1, further comprising defining at least a portion of the inter-core communication wires to configure the cores of the multi-core die to communicate with one another for performing power management of the multi-core die.

7. The method of claim 6, wherein said performing power management of the multi-core die comprises synchronizing power state changes by the cores.

8. The method of claim 6, wherein said performing power management of the multi-core die comprises management of a shared voltage source.

9. The method of claim 6, wherein said performing power management of the multi-core die comprises management of a shared clock source.

10. The method of claim 1, further comprising defining at least a portion of the inter-core communication wires as an internal bypass bus for bypassing an external bus for interconnecting the multi-core die to a chipset.

11. The method of claim 10, wherein the cores are defined to be configured so that when one of the cores drives the external bus, the other cores listen via the internal bypass bus rather than the external bus.

12. The method of claim 1, wherein the first reticle set is usable to print an M×

N matrix of Q-core dies, wherein the second reticle set is usable to print (N×

M)/2 P-core dies, wherein M is an even number at least 2 and N is at least 1.

13. The method of claim 1, wherein the first reticle set is usable to print an M×

N matrix of Q-core dies, wherein the second reticle set is useable to print both P-core dies and Q-core dies.

14. The method of claim 13, wherein the second reticle set is usable to print N×

[(M−

1)/2] P-core dies and M Q-core dies, wherein M is an odd number at least 3 and N is at least 2.

15. The method of claim 13, wherein the second reticle set is usable to print (N×

M)/4 P-core dies and (N×

M)/2 Q-core dies, wherein M is an even number at least 4 and N is at least 2.

16. The method of claim 1, wherein said modifying less than all of the reticles of the first reticle set to produce the second reticle set comprises modifying only non-transistor layers of the first reticle set.

17. The method of claim 1, wherein said modifying less than all of the reticles of the first reticle set to produce the second reticle set comprises modifying fewer than half of the layers of the first reticle set.

18. Multi-core dies produced by a process comprising:

developing a first reticle set usable to print Q-core dies, wherein the first reticle set defines scribe lines to separate the Q-core dies, wherein the scribe lines collectively define a seal ring to surround each Q-core die, wherein Q is at least 1; and

modifying less than all of the reticles of the first reticle set to produce a second reticle set useable to print P-core dies, wherein said modifying comprises removing at least one defined scribe line of the first reticle set and defining inter-core communication wires to connect at least two adjacent cores that would have been separated by the replaced scribe line, wherein P is at least twice Q;

printing the multi-core dies on a semiconductor wafer using the second reticle set; and

cutting the multi-core dies on the semiconductor wafer along the remaining scribe lines.

19. The multi-core dies of claim 18, wherein:

the wires enable the at least two connected cores to communicate during operation; and

the wires are not connected to physical input/output landing pads of the P-core die such that they do not carry signals through the inter-core communication wires off the P-core die.

20. The multi-core dies of claim 18, wherein at least a portion of the wires are employed to enable the cores of the multi-core die to communicate with one another for performing power management of the multi-core die.

21. The multi-core dies of claim 18, wherein at least a portion of the wires are employed as an internal bypass bus for bypassing an external bus for interconnecting the multi-core die to a chipset and that supports a multi-processor protocol.

22. The multi-core dies of claim 18, wherein the first reticle set is usable to print an M×

N matrix of Q-core dies, wherein the second reticle set is usable to print (N×

M)/2 P-core dies, wherein M is an even number at least 2 and N is at least 1.

23. The multi-core dies of claim 18, wherein the first reticle set is usable to print an M×

N matrix of Q-core dies, wherein the modified second reticle set is useable to print both P-core dies and Q-core dies.

24. The multi-core dies of claim 23, wherein the second reticle set is usable to print N×

[(M−

1)/2] P-core dies and M Q-core dies, wherein M is an odd number at least 3 and N is at least 2.

25. The multi-core dies of claim 23, wherein the second reticle set is usable to print (N×

M)/4 P-core dies and (N×

M)/2 Q-core dies, wherein M is an even number at least 4 and N is at least 2.

26. The multi-core dies of claim 18, wherein said modifying less than all of the reticles of the first reticle set to produce the second reticle set comprises modifying only non-transistor layers of the first reticle set.

27. The multi-core dies of claim 18, wherein said modifying less than all of the reticles of the first reticle set to produce the second reticle set comprises modifying fewer than half of the layers of the first reticle set.