FREQUENCY DOUBLER, A DEVICE INCLUDING THE SAME AND A METHOD FOR FREQUENCY DOUBLING

• US 20120161824A1
• Filed: 01/10/2011
• Published: 06/28/2012
• Est. Priority Date: 12/28/2010
• Status: Active Grant

• Current Assignee: Beken Corporation
• Original Assignee: Beken Corporation
• Inventors: Tao, Yunbin, Liu, Jiazhou
• Granted Patent: US 8,269,530 B2
• Time in Patent Office: Days
• US Class Current: 327/122
• CPC Class Codes: H03K 19/00346 Modifications for eliminating interference or parasitic voltages or currents
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00052 by mixing the outputs of fixed delayed signals with each other or with the input signal
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

A frequency doubler comprises: a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal; a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

Claims

1. A frequency doubler, comprising:

a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and a second non-overlapping signal, each of the first and second non-overlapping signals having a frequency of the first signal, wherein an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined by the first control signal;

a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal.

2. The frequency doubler of claim 1, wherein the combination circuit comprises an OR gate.

3. The frequency doubler of claim 1, wherein the non-overlapping signal generation circuit comprises:

an input module configured to receive the first signal and generate a first and a second clock signal according to the first signal;

a first controllable delay module configured to receive the first clock signal and the first control signal, apply a first delay determined at least partly by the first control signal to the first clock signal so as to generate a first delayed signal;

a second controllable delay module configured to receive the second clock signal and the first control signal, apply a second delay determined at least partly by the first control signal to the second clock signal so as to generate a second delayed signal;

wherein the input module is further configured to receive the first and second delayed signals and generate the first and second clock signals according to the first signal, the first delayed signals and the second delayed signal;

an output module, configured to receive the first delayed signal and generate the first non-overlapping signal accordingly, receive the second delayed signal and generate the second non-overlapping signal accordingly.

4. The frequency doubler of claim 3, wherein the input module includes a first inverter, a second inverter, a third inverter, a first NAND gate and a second NAND gate, wherein an input end of the first inverter and an input end of the first NAND gate are configured to receive the first signal, another input end of the first NAND gate is configured to receive the second delayed signal, an output end of the first inverter is connected to an input end of the second NAND gate, another input end of the second NAND gate is configured to receive the first delayed signal, an output end of the first NAND gate is connected to an input end of the second inverter, an output end of the second NAND gate is connected to an input end of the third inverter, the second inverter is configured to output the first clock signal, the third inverter is configured to output the second clock signal;

the output module includes a fourth inverter and a fifth inverter, wherein an input end of the fourth inverter is configured to receive the first delayed signal, an input end of the fifth inverter is configured to receive the second delayed signal, the fourth inverter is configured to output the first non-overlapping signal, the fifth inverter is configured to output the second non-overlapping signal.

5. The frequency doubler of claim 3, wherein the first controllable delay module and the second delay module are jointly configured to:

when a voltage of the first control signal increases, decrease a duty ratio of the first non-overlapping signal and a duty ratio of the second non-overlapping signal, and

when a voltage of the first control signal decreases, increase a duty ratio of the first non-overlapping signal and a duty ratio of the second non-overlapping signal.

6. The frequency doubler of claim 3, wherein the first controllable delay module includes:

a first P-type MOSFET, a first N-type MOSFET, a second N-type MOSFET and a first capacitor, a source of the first P-type MOSFET is provided with a positive working voltage, a gate of the first P-type MOSFET and a gate of the first N-type MOSFET are configured to receive the first clock signal, a source of the first N-type MOSFET is connected with a drain of the second N-type MOSFET, a drain of the first P-type MOSFET is connected with a drain of a first N-type MOSFET and a terminal of the first capacitor to generate the first delayed signal, a source of the second N-type MOSFET and another terminal of the first capacitor are grounded, a gate of the second N-type MOSFET is configured to receive the first control signal.

7. The frequency doubler of claim 3, wherein the second delay module includes a second P-type MOSFET, a third N-type MOSFET, a fourth N-type MOSFET and a second capacitor, a source of the second P-type MOSFET is provided with a positive working voltage, a gate of the second P-type MOSFET and a gate of the third N-type MOSFET are configured to receive the second clock signal, a source of the third N-type MOSFET is connected with a drain of the fourth N-type MOSFET, a drain of the second P-type MOSFET is connected with a drain of a third N-type MOSFET and a terminal of the second capacitor to generate the second delayed signal, a source of the fourth N-type MOSFET and another terminal of the second capacitor are grounded, a gate of the fourth N-type MOSFET is configured to receive the first control signal.

8. The frequency doubler of claim 3, wherein in the non-overlapping signal generation circuit, elements with corresponding functions have approximately the same electrical parameters.

9. The frequency doubler of claim 1, further comprising:

a first feedback circuit configured to receive the frequency-doubled signal and a first reference signal, use the frequency-doubled signal and the first reference signal to generate the first control signal.

10. The frequency doubler of claim 9, wherein the first feedback circuit comprises:

a first error amplifier configured to receive a first reference signal and the frequency-doubled signal, generate the first control signal according to an error between a voltage of the first reference signal and an average voltage of the frequency-doubled signal.

11. The frequency doubler of claim 10, wherein the voltage of the first reference signal is adjustable.

12. The frequency doubler of claim 1, further comprising:

a duty cycle changing circuit configured to receive a second signal and change a duty cycle of the second signal to a preset value, so as to generate the first signal.

13. The frequency doubler of claim 12, wherein the preset value is about 50%.

14. The frequency doubler of claim 12, wherein the duty cycle changing circuit comprises:

a pulse generator configured to receive the second signal and use the second signal to generate a pulse sequence signal;

a charge and discharge circuit configured to receive the pulse sequence signal and a second control signal, change a voltage at an output end of the charge and discharge circuit according to the pulse sequence signal at a speed which is at least partly determined by the second control signal;

an analog-to-digital converter connected to the output end of the charge and discharge circuit and convert an output of the charge and discharge circuit from analog to digital, so as to generate the first signal.

15. The frequency doubler of claim 14, wherein the voltage at the output end of the charge and discharge circuit decreases at a speed at least partly determined by the second control signal.

16. The frequency doubler of claim 14, wherein the charge and discharge circuit comprises a third P-type MOSFET, a fifth N-type MOSFET, a sixth N-type MOSFET and a third capacitor,

a gate of the third P-type MOSFET and a gate of the fifth N-type MOSFET are connected with each other and configured to receive the pulse sequence signal, a source of the third P-type MOSFET and a terminal of the third capacitor are connected with each other and provided with the positive working voltage, a drain of the third P-type MOSFET is connected with a drain of the fifth N-type MOSFET and another terminal of the third capacitor to form the output end of the charge and discharge circuit, a source of the fifth N-type MOSFET is connected with a drain of the sixth N-type MOSFET, a gate of the sixth N-type MOSFET is configured to receive the second control signal, a source of the sixth N-type MOSFET is grounded.

17. The frequency doubler of claim 14, wherein the duty changing circuit further comprises:

a second feedback circuit configured to receive the generated first signal and a second reference signal, use the first signal and the second reference signal to generate the second control signal.

18. The frequency doubler of claim 17, wherein the second feedback circuit comprises:

a second error amplifier configured to receive the second reference signal and the first signal, change a voltage at an output end of the second error amplifier according to an error between a voltage of the second reference signal and an average voltage of the first signal.

19. The frequency doubler of claim 17, wherein the voltage of the second reference signal is adjustable.

20. A method, comprising:

receiving a first signal with a frequency doubler, the frequency doubler including;

a non-overlapping signal generation circuit configured to receive a first signal and a first control signal and generate a first and second non-overlapping signals, each of the first and second non-overlapping signals has a frequency of the first signal, an average of a duty cycle of the first non-overlapping signal and a duty cycle of the second non-overlapping signal is determined at least partly by the first control signal;

a combination circuit configured to receive and combine the two non-overlapping signals to generate a frequency-doubled signal;

doubling a frequency of the first signal with the frequency doubler.

21. The method of claim 20, wherein the frequency doubler further includes a first feedback circuit configured to receive the frequency-doubled signal and a first reference signal, use the frequency-doubled signal and the first reference signal to generate the first control signal.

22. The method of claim 20, wherein the frequency doubler further includes a duty cycle changing circuit configured to receive a second signal and change a duty cycle of the second signal to a preset value, so as to generate the first signal.