SIGNAL PROCESSING CIRCUIT
First Claim
1. A signal processing circuit comprising:
- a control unit;
an arithmetic unit; and
a buffer memory device,wherein the buffer memory device stores data sent from a main memory device or the arithmetic unit in accordance with an instruction from the control unit,wherein the buffer memory device comprises a plurality of memory cells, andwherein the memory cells each comprise;
a transistor comprising an oxide semiconductor in a channel formation region; and
a memory element to which charge whose amount depends on a value of the data is supplied via the transistor.
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Accused Products
Abstract
It is an object to provide a signal processing circuit for which a complex manufacturing process is not necessary and whose power consumption can be suppressed. In particular, it is an object to provide a signal processing circuit whose power consumption can be suppressed by stopping the power supply for a short time. The signal processing circuit includes a control circuit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit; the buffer memory device comprises a plurality of memory cells; and the memory cells each include a transistor including an oxide semiconductor in a channel formation region and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor.
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Citations
24 Claims
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1. A signal processing circuit comprising:
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a control unit; an arithmetic unit; and a buffer memory device, wherein the buffer memory device stores data sent from a main memory device or the arithmetic unit in accordance with an instruction from the control unit, wherein the buffer memory device comprises a plurality of memory cells, and wherein the memory cells each comprise; a transistor comprising an oxide semiconductor in a channel formation region; and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A signal processing circuit comprising:
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a control unit; an arithmetic unit; a buffer memory device; and a main memory device, wherein the buffer memory device stores data sent from the main memory device or the arithmetic unit in accordance with an instruction from the control unit, wherein the buffer memory device comprises a plurality of memory cells, and wherein the memory cells each comprise; a transistor comprising an oxide semiconductor in a channel formation region; and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A signal processing circuit comprising:
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a control unit; an arithmetic unit; and a buffer memory device, wherein the buffer memory device stores data including an instruction sent from a main memory device, wherein the control unit reads the data from the buffer memory device and controls operations of the arithmetic unit and the buffer memory device in accordance with the instruction, wherein the buffer memory device comprises a plurality of memory cells, and wherein the memory cells each comprise; a transistor comprising an oxide semiconductor in a channel formation region; and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A signal processing circuit comprising:
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a control unit; an arithmetic unit; a buffer memory device; and a main memory device, wherein the buffer memory device stores data including an instruction sent from the main memory device, wherein the control unit reads the data from the buffer memory device and controls operations of the arithmetic unit and the buffer memory device in accordance with the instruction, wherein the buffer memory device comprises a plurality of memory cells, and wherein the memory cells each comprise; a transistor comprising an oxide semiconductor in a channel formation region; and a memory element to which charge whose amount depends on a value of the data is supplied via the transistor. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification