Power Managed Lock Optimization

• US 20120167107A1
• Filed: 03/07/2012
• Published: 06/28/2012
• Est. Priority Date: 05/13/2009
• Status: Active Grant

• Current Assignee: Bernard J. Semeria, Josh P De Cesare, Michael J. Smith, Puneet Kumar, Ruchi Wadhawan
• Original Assignee: Bernard J. Semeria, Josh P De Cesare, Michael J. Smith, Puneet Kumar, Ruchi Wadhawan
• Inventors: de Cesare, Josh P., Wadhawan, Ruchi, Smith, Michael J., Kumar, Puneet, Semeria, Bernard J.
• Granted Patent: US 8,332,559 B2
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms

Abstract

In an embodiment, a timer unit may be provided that may be programmed to a selected time interval, or wakeup interval. A processor may execute a wait for event instruction, and enter a low power state for the thread that includes the instruction. The timer unit may signal a timer event at the expiration of the wakeup interval, and the processor may exit the low power state in response to the timer event. The thread may continue executing with the instruction following the wait for event instruction. In an embodiment, the processor/timer unit may be used to implement a power-managed lock acquisition mechanism, in which the processor is awakened a number of times to check the lock and execute the wait for event instruction if the lock is not free, after which the thread may block until the lock is free.

Claims

1. A method comprising:

a processor attempting to acquire a lock for a thread being executed;

responsive to failing to acquire the lock, determining that at least one additional iteration of attempting to acquire the lock is permitted for the thread;

responsive to determining that the additional iteration is permitted, waiting for an event prior to initiating another iteration, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption; and

responsive to determining that the additional iteration is permitted, permitting the thread to remain scheduled on the processor.

2. The method as recited in claim 1 further comprising:

the processor detecting the event;

the processor exiting the low power state; and

the processor performing the additional iteration.

3. The method as recited in claim 2 wherein the performing the additional iteration comprises:

the processor attempting to acquire the lock for the thread;

responsive to failing to acquire the lock, determining that yet another iteration of attempting to acquire the lock is not permitted for the thread; and

descheduling the thread.

4. The method as recited in claim 3 further comprising:

a thread scheduler detecting that the thread is descheduled waiting for the lock;

the thread scheduler detecting that the lock is released; and

the thread scheduler marking the thread as eligible to schedule responsive to detecting that the lock is released.

5. The method as recited in claim 2 wherein the performing the additional iteration comprises:

the processor attempting to acquire a lock for the thread;

responsive to acquiring the lock, the processor performing processing on a resource controlled by the lock; and

responsive to completing the processing, the processor releasing the lock.

6. A computer accessible storage medium storing a plurality of instructions which, when executed by a processor, cause the processor to:

attempt to acquire a lock for a thread being executed;

responsive to failing to acquire the lock, determine that a reattempt to acquire the lock is permitted for the thread;

responsive to determining that the reattempt is permitted, wait for an event prior to initiating the reattempt, wherein the waiting causes the processor to enter a low power state; and

responsive to determining that the reattempt is permitted, leaving the thread scheduled on the processor.

7. The computer accessible storage medium as recited in claim 6 wherein the plurality of instructions include instructions executed in response to the processor detecting the event and exiting the lower power state, the instructions causing the processor to perform the reattempt.

8. The computer accessible storage medium as recited in claim 7 wherein the instructions which, when executed, perform the reattempt comprise instructions which, when executed:

attempt to acquire the lock for the thread;

responsive to failing to acquire the lock, determine that yet another reattempt is not permitted for the thread; and

block the thread.

9. The computer accessible storage medium as recited in claim 8 further comprising a second plurality of instructions comprises a thread scheduler, and wherein the thread scheduler is executable on the processor to:

detect that the thread is blocked waiting for the lock;

detect that the lock is released; and

mark the thread as eligible to schedule responsive to detecting that the lock is released.

10. The computer accessible storage medium as recited in claim 7 wherein the instructions which, when executed, perform the reattempt comprise instructions which, when executed:

attempt to acquire a lock for the thread;

responsive to acquiring the lock, perform processing on a resource controlled by the lock; and

responsive to completing the processing, release the lock.

11. A method comprising:

performing a plurality of iterations of;

attempting to acquire a lock for a thread; and

waiting for an event responsive to failing to acquire the lock, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption;

subsequent to performing the plurality of iterations without acquiring the lock, descheduling the thread.

12. The method as recited in claim 11 further comprising the processor exiting the low power state responsive to the event, wherein the event occurs in response to the expiration of a predetermined time period, and wherein a number of the plurality of iterations multiplied by the predetermined time period is approximately an amount of time that the lock is expected to be held for processing of a resource associated with the lock.

13. The method as recited in claim 11 wherein each of the plurality of iterations further comprises:

updating an iteration count; and

testing the iteration count for expiration, wherein expiration of the iteration count indicates that the plurality of iterations are complete.

14. The method as recited in claim 11 further comprising:

during thread scheduling, detecting that the thread is descheduled waiting for the lock;

detecting that the lock is released; and

rescheduling the thread.

15. The method as recited in claim 14 further comprising, responsive to the rescheduling:

performing the plurality of iterations of;

attempting to acquire the lock for a thread; and

waiting for the event responsive to failing to acquire the lock, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption;

subsequent to performing the plurality of iterations without acquiring the lock, descheduling the thread again.

16. The method as recited in claim 14 further comprising, responsive to the rescheduling:

acquiring the lock; and

performing processing on a resource, wherein access to the resource is controlled by the lock.

17. A computer accessible storage medium storing a plurality of instructions which, when executed by a processor, cause the processor to:

perform a plurality of iterations of;

attempting to acquire a lock for a thread; and

waiting for an event responsive to failing to acquire the lock, wherein waiting for the event causes the processor to enter a low power state, reducing power consumption;

subsequent to performing the plurality of iterations without acquiring the lock, block the thread.

18. The computer accessible storage medium as recited in claim 17 further comprising the processor exiting the low power state responsive to the event, wherein the event occurs in response to the expiration of a predetermined time period, and wherein a number of iterations multiplied by the predetermined time period is approximately an amount of time that the lock is expected to be held.

19. The computer accessible storage medium as recited in claim 17 wherein the instructions executed during each of the plurality of iterations include instructions which, when executed by the processor, cause the processor to:

update an iteration count; and

test the iteration count for expiration, wherein the expiration of the iteration count indicates that the plurality of iterations are complete.

20. The computer accessible storage medium as recited in claim 17 further comprising a thread scheduler which, when executed:

detects that the thread is blocked waiting for the lock;

detects that the lock is released; and

reschedules the thread.