One-Transistor Pixel Array with Cascoded Column Circuit

• US 20120168307A1
• Filed: 03/15/2012
• Published: 07/05/2012
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith
• Granted Patent: US 8,524,487 B2
• Time in Patent Office: Days
• US Class Current: 204/406
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.

Claims

1. A device comprising:

an array of pixels, at least some pixels in the array of pixels comprising;

a chemically-sensitive field-effect transistor (chemFET) including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer; and

a cascode transistor including a source terminal, a drain terminal and a gate terminal, wherein the source terminal of the cascode transistor is directly connected to the drain terminal of the chemFET; and

a plurality of column lines and a plurality of row lines coupled to pixels in the array of pixels, wherein each column line in the plurality of column lines is directly connected to drain terminals of cascode transistors of a corresponding first plurality of pixels in the array, and wherein each row line in the plurality of row lines is directly connected to the source terminals of chemFETs of a corresponding second plurality of pixels in the array; and

2. The device of claim 1, further comprising circuitry coupled to the plurality of column lines and row lines for reading a selected pixel connected to a selected column line and a selected row line, the circuitry comprising:

bias circuitry to apply a read voltage to the selected row line, and to apply a bias voltage to the gate terminal of the cascode transistor of the selected pixel; and

sense circuitry to read the selected pixel based on a sampled voltage level on the selected column line.

3. The device of claim 2, wherein the sampled voltage level on the selected column line is established based a threshold voltage of the chemFET of the selected pixel.

4. The device of claim 2, wherein the sampled voltage level indicates an ion-concentration of an analyte solution coupled to the floating gate of the chemFET of the selected pixel via the passivation layer.

5. The device of claim 2, wherein:

the bias circuitry applies the read voltage to the selected row line and applies the bias voltage to the gate terminal of the cascode transistor of the selected pixel during a read interval; and

the sense circuitry includes;

a pre-charge circuit to pre-charge the selected column line to a pre-charge voltage level prior to the read interval; and

a sample circuit to sample a voltage level on the selected column line during the read interval.

6. The device of claim 5, wherein the sample circuit includes a sample and hold circuit to hold an analog value of a voltage on the selected column line during the read interval, and an analog to digital converter to convert the analog value to a digital value.

7. The device of claim 5, wherein the sample circuit includes an analog to digital converter to directly convert a voltage on the selected column line to a digital value during the read interval.

8. The device of claim 5, wherein the pre-charge circuit includes a switch between the selected column line and a reference voltage, the switch responsive to a switching voltage to turn on prior to the read interval to pre-charge the selected column line to the pre-charge voltage level, and to turn off the switch during the read interval.

9. The device of claim 1, wherein a given pixel in the array of pixels further comprises a current source coupled to the drain terminal of the cascode transistor of the given pixel.

10. A device comprising:

an array of chemically-sensitive field-effect transistors (chemFETs), at least some chemFETs in the array of chemFETs including a source terminal and a drain terminal, and a floating gate coupled to a passivation layer;

a plurality of column lines and a plurality of row lines coupled to chemFETs in the array of chemFETs, wherein each column line in the plurality of column lines is directly connected to drain terminals of a corresponding plurality of chemFETs in the array, and each row line in the plurality of row lines is directly connected to source terminals of a corresponding second plurality of chemFETs in the array; and

respective cascode transistors coupled to corresponding column lines in the plurality of column lines, wherein a given cascode transistor includes a source terminal, a drain terminal and a gate terminal, and the source terminal of the given cascode transistor is coupled to the corresponding column line.

11. The device of claim 10, further comprising circuitry coupled to the column lines and row lines for reading a selected chemFET connected to a selected column line and a selected row line, the circuitry comprising:

bias circuitry to apply a read voltage to the selected row line, and to apply a bias voltage to the gate terminal of a selected cascode transistor coupled to the selected column line; and

sense circuitry to read the selected chemFET based on a sampled voltage level at the drain terminal of the selected cascode transistor.

12. The device of claim 11, wherein the sampled voltage level at the drain terminal of the selected cascode transistor is established based on a threshold voltage of the chemFET of the selected pixel.

13. The device of claim 10, wherein the sampled voltage level indicates an ion-concentration of an analyte solution coupled to the floating gate of the chemFET of the selected pixel via the passivation layer.

14. The device of claim 11, further comprising respective current sources coupled to the drain terminals of the cascode transistors.

15. The device of claim 11, wherein:

the bias circuitry applies the read voltage to the selected row line and applies the bias voltage to the gate terminal of the cascode transistor during a read interval; and

the sense circuitry includes;

a pre-charge circuit to pre-charge the selected column line to a pre-charge voltage level prior to the read interval; and

a sample circuit to sample a voltage level at the drain terminal of the selected cascode transistor during the read interval.

16. The device of claim 15, wherein the sample circuit includes a sample and hold circuit to hold an analog value of a voltage at the drain terminal of the selected cascode transistor during the read interval, and an analog to digital converter to convert the analog value to a digital value.

17. The device of claim 15, wherein the sample circuit includes an analog to digital converter to directly convert a voltage at the drain terminal of the selected cascode transistor to a digital value during the read interval.

18. The device of claim 15, wherein the pre-charge circuit includes a switch between the selected column line and a reference voltage, the switch responsive to a switching voltage to turn on prior to the read interval to pre-charge the selected column line to the pre-charge voltage level, and to turn off the switch during the read interval.