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MEMORY-AWARE SCHEDULING FOR NUMA ARCHITECTURES

  • US 20120174117A1
  • Filed: 12/29/2010
  • Published: 07/05/2012
  • Est. Priority Date: 12/29/2010
  • Status: Active Grant
First Claim
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1. A system including instructions recorded on a computer-readable medium, the system comprising:

  • a topology reader configured to determine a topology of a Non-Uniform Memory Access (NUMA) architecture including a number of, and connections between, a plurality of sockets, each socket including one or more cores and at least one memory configured to execute a plurality of threads of a software application;

    a core list generator configured to generate, for each designated core of the NUMA architecture, and based on the topology, a proximity list listing non-designated cores in an order corresponding to a proximity of the non-designated cores to the designated core; and

    a core selector configured to determine, at a target core and during the execution of the plurality of threads, that the target core is executing an insufficient number of the plurality of threads, and further configured to select a source core at the target core, according to the proximity list associated therewith, for subsequent transfer of a transferred thread from the selected source core to the target core for execution thereon.

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