SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20120175608A1
• Filed: 01/09/2012
• Published: 07/12/2012
• Est. Priority Date: 01/12/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 8,921,948 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/469 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After-treatment of these layers
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

The semiconductor device includes a gate electrode over a substrate, a gate insulating layer over the gate electrode, an oxide semiconductor layer over the gate insulating layer, and a source electrode and a drain electrode over the oxide semiconductor layer. A length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times, preferably more than five times as long as a channel length of the semiconductor device. Further, oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by heat treatment. In addition, an insulating layer is formed after the oxide semiconductor layer is selectively etched.

Claims

1. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer; and

a source electrode and a drain electrode over the oxide semiconductor layer,

wherein a length of part of an outer edge of the oxide semiconductor layer from an outer edge of the source electrode to an outer edge of the drain electrode is more than three times as long as a channel length of the semiconductor device.

2. The semiconductor device according to claim 1, wherein the length of the part of the outer edge of the oxide semiconductor layer from the outer edge of the source electrode to the outer edge of the drain electrode is more than five times as long as the channel length of the semiconductor device.

3. The semiconductor device according to claim 1, further comprising an insulating film containing oxygen over the oxide semiconductor layer, the source electrode and the drain electrode, wherein the insulating film covers a side surface of the oxide semiconductor layer.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is non-single-crystal.

6. The semiconductor device according to claim 1, wherein part of the outer edge of the oxide semiconductor layer and part of an outer edge of the source electrode are aligned, and wherein part of the outer edge of the oxide semiconductor layer and part of an outer edge portion of the drain electrode are aligned.

7. A semiconductor device comprising:

a gate electrode over a substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer; and

a source electrode and a drain electrode over the oxide semiconductor layer;

wherein total length of parts of an outer edge of the oxide semiconductor layer which does not overlap with the source electrode and the drain electrode is more than six times as long as a channel length of the semiconductor device.

8. The semiconductor device according to claim 7, wherein the total length of the parts of the outer edge of the oxide semiconductor layer which does not overlap with the source electrode and the drain electrode is more than ten times as long as the channel length of the semiconductor device.

9. The semiconductor device according to claim 7, further comprising an insulating film containing oxygen over the oxide semiconductor layer, the source electrode and the drain electrode, wherein the insulating film covers a side surface of the oxide semiconductor layer.

10. The semiconductor device according to claim 7, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

11. The semiconductor device according to claim 7, wherein the oxide semiconductor layer is non-single-crystal.

12. The semiconductor device according to claim 7, wherein part of the outer edge of the oxide semiconductor layer and part of an outer edge of the source electrode are aligned, and wherein part of the outer edge of the oxide semiconductor layer and part of an outer edge portion of the drain electrode are aligned.

13. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer;

performing heat treatment after the oxide semiconductor layer is formed;

forming a source electrode and a drain electrode over the oxide semiconductor layer after the heat treatment;

forming a resist mask over the oxide semiconductor layer, the source electrode and the drain electrode, wherein the resist mask overlaps with the gate electrode;

etching the oxide semiconductor layer selectively using the resist mask, wherein the source electrode and the drain electrode are also used as a mask for the etching step; and

forming an insulating layer so as to cover the oxide semiconductor layer, the source electrode, and the drain electrode after the etching is performed.

14. The method for manufacturing a semiconductor device, according to claim 13, wherein the gate insulating layer contains excessive oxygen with respect to a stoichiometry proportion.

15. The method for manufacturing a semiconductor device, according to claim 13, wherein oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by the heat treatment.

16. The method for manufacturing a semiconductor device, according to claim 13, wherein the heat treatment is performed at higher than or equal to 300°

C. and lower than or equal to 450°

C.

17. The method for manufacturing a semiconductor device, according to claim 13, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

18. The method for manufacturing a semiconductor device, according to claim 13, wherein the oxide semiconductor layer is non-single-crystal.

19. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer;

forming a conductive layer over the oxide semiconductor layer;

performing heat treatment after the oxide semiconductor layer is formed;

forming a first mask over the conductive layer;

forming a source electrode and a drain electrode by etching the conductive layer selectively using the first mask;

forming a second mask overlapping with the gate electrode, part of the source electrode and part of the drain electrode after removing the first mask;

etching the oxide semiconductor layer selectively using the second mask, wherein part of the source electrode and part of the drain electrode which does not overlap with the second mask are also used as a mask for the etching step; and

forming an insulating layer so as to cover the oxide semiconductor layer, the source electrode, and the drain electrode after the etching is performed.

20. The method for manufacturing a semiconductor device, according to claim 19, wherein the heat treatment is performed after the conductive layer is formed.

21. The method for manufacturing a semiconductor device, according to claim 19, wherein the gate insulating layer contains excessive oxygen with respect to a stoichiometry proportion.

22. The method for manufacturing a semiconductor device, according to claim 19, wherein oxygen is supplied from the gate insulating layer to the oxide semiconductor layer by the heat treatment.

23. The method for manufacturing a semiconductor device, according to claim 19, wherein the heat treatment is performed at higher than or equal to 300°

C. and lower than or equal to 450°

C.

24. The method for manufacturing a semiconductor device, according to claim 19, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, and Zn.

25. The method for manufacturing a semiconductor device, according to claim 19, wherein the oxide semiconductor layer is non-single-crystal.