ALIGNMENT MARKS TO ENABLE 3D INTEGRATION

• US 20120175789A1
• Filed: 01/10/2011
• Published: 07/12/2012
• Est. Priority Date: 01/10/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Hannon, Robert, Kinser, Emily R., Landers, William F., Volant, Richard P., Winstel, Kevin R., Graves-Abe, Troy L., Patrarca, Kevin S.
• Granted Patent: US 8,546,961 B2
• Time in Patent Office: Days
• US Class Current: 257/797
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/29187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/29188
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/92 Specific sequence of method steps
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/1431 Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]

Abstract

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Claims

1. A method of forming alignment marks to enable three dimensional (3D) structures comprising:

forming apertures in a first surface of a first semiconductor substrate;

bonding the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate;

thinning the first semiconductor substrate on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and

aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

2. A method of forming alignment marks to enable three dimensional (3D) structures comprising:

obtaining a first semiconductor substrate and a second semiconductor substrate;

forming apertures in a first surface of the first semiconductor substrate;

bonding the first surface of the first semiconductor substrate to a first surface of the second semiconductor substrate;

thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and

aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

3. The method of claim 2 further comprising forming an alignment mark on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

4. The method of claim 2 wherein the apertures are at least partially filled and thinning the first semiconductor substrate exposes the filled apertures.

5. The method of claim 2 wherein the apertures are at least partially filled and thinning the first semiconductor substrate to leave a thin layer of first semiconductor substrate over the apertures to optically expose the apertures.

6. The method of claim 2 wherein the apertures are only partially filled.

7. The method of claim 2 wherein the apertures are completely filled.

8. The method of claim 2 wherein forming the apertures comprises forming the apertures only part way through the first semiconductor substrate.

9. The method of claim 2 wherein filling the apertures comprises:

depositing a liner of a first material in the aperture; and

depositing a conformal layer of a second material over the liner, wherein the conformal layer does not fill the aperture.

10. The method of claim 9 wherein the thinning of the first semiconductor on a second surface includes removing the liner from the filled apertures and leaving the conformal layer exposed.

11. The method of claim 9 wherein the first material is titanium nitride or a combination of tantalum and tantalum nitride and the second material is selected from the group consisting of tungsten, polycrystalline silicon, oxide, oxide/nitride, silicides, copper, tantalum/tantalum nitride, ruthenium and titanium/titanium nitride.

12. The method of claim 2 wherein the feature is a via extending from the second surface of the first semiconductor substrate into the first semiconductor substrate.

13. The method of claim 9 further comprising depositing a dielectric over the aperture which closes off the aperture but does not fill it.

14. The method of claim 9 wherein the apertures are bottle shaped having a reduced opening at an open end of the apertures and wherein the depositing of the conformal layer closes off the apertures.

15. The method of claim 9 further comprising depositing a nonconformal layer of the second material over the apertures to close off the apertures.

16. The method of claim 9 wherein after depositing a conformal layer further comprising depositing a third material to completely fill the apertures, wherein the third material is a dielectric material.

17. The method of claim 2 further comprising joining a third semiconductor substrate to the second surface of the first semiconductor substrate using the filled apertures as alignment marks to align the third semiconductor substrate with the second surface of the first semiconductor substrate.

18. A semiconductor structure comprising a semiconductor substrate having an alignment mark on a first surface of the semiconductor substrate that continues through the semiconductor substrate to a second surface of the semiconductor substrate.

19. The semiconductor structure of claim 18 wherein the alignment mark comprises an aperture that is unfilled.

20. The semiconductor structure of claim 19 wherein the aperture is partly filled, the aperture having a central hollow space.

21. The semiconductor structure of claim 19 wherein the aperture is completely filled.

22. A semiconductor structure comprising:

a first semiconductor substrate having a first and a second surface, the first semiconductor substrate having apertures extending from the first surface to the second surface;

a second semiconductor substrate having a first surface, wherein the first surface of the first semiconductor substrate is bonded to the first surface of the second semiconductor substrate; and

a feature formed on the second surface of the first semiconductor substrate using the apertures in the second surface as an alignment mark for the formed feature.

23. The semiconductor structure of claim 22 wherein the apertures are partly filled, the apertures having a central hollow space.

24. The semiconductor structure of claim 22 wherein the apertures are completely filled.

25. The semiconductor structure of claim 22 wherein the apertures are unfilled.