STATE-MONITORING MEMORY ELEMENT

• US 20120176854A1
• Filed: 11/22/2011
• Published: 07/12/2012
• Est. Priority Date: 04/17/2007
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Sheets, Michael, Williams, Timothy
• Granted Patent: US 8,462,576 B2
• Time in Patent Office: Days
• US Class Current: 365/226
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be disturbed in different locations on the IC for better coverage.

Claims

1-20. -20. (canceled)

21. An system, comprising:

a first circuit comprising memory elements of a memory array that are powered at an input supply voltage, wherein the input supply voltage changes over time; and

a second circuit coupled to a state-monitoring memory element of the memory array, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array, wherein the second circuit is configured to determine if the input supply voltage drops below a threshold voltage at which the state-monitory memory element operates.

22. The system of claim 21, wherein the second circuit comprises a voltage supply circuit configured to provide a degraded input supply voltage to the state-monitoring memory element and to provide the input supply voltage to the other memory elements of the memory array, wherein the degraded input supply voltage is less than the input supply voltage.

23. The system of claim 21, wherein the second circuit comprises a circuit to provide a degraded ground to the state-monitoring memory element.

24. The system of claim 21, wherein the state-monitoring memory element is substantially identical to one or more of the other memory elements of the memory array.

25. The system of claim 22, wherein the state-monitoring memory element comprises a reduced ability to retain a logic state compared to one of the other memory elements, and wherein the state-monitoring memory element is configured to lose the logic state before the one memory element when the degraded input supply voltage drops below the threshold voltage.

26. The system of claim 25, wherein the second circuit further comprises a voltage supply circuit configured to supply the degraded input supply voltage to the state-monitoring memory element to have the reduced ability.

27. The system of claim 26, wherein the second circuit further comprises a failure detection element configured to detect a failure by the state-monitoring memory element to retain the logic state and responsive to the detection to generate an indicator of the failure, and wherein the failure detection element is further configured to issue an interrupt signal to a system processor.

28. The system of claim 27, wherein the voltage supply circuit comprises one of a diode, a transistor, or a combination thereof.

29. The system of claim 21, wherein the state-monitoring memory element is one of a register, a memory cell, a latch, an array of registers, or an array of memory cells.

30. The system of claim 27, wherein the second circuit further comprises a logic analyzer, wherein the logic analyzer is configured to generate an indicator of failure if the state-monitoring memory element fails to maintain the initial logic state when the input voltage drops below the threshold voltage.

31. The system of claim 30, wherein the logic analyzer is adapted to issue a reset signal responsive to detecting a failure in the state-monitoring memory element.

32. The system of claim 21, further comprising at least one current source coupled to the state-monitoring memory element.

33. The system of claim 21, wherein the first circuit and the second circuit reside on a common integrated circuit.

34. A method, comprising:

powering a first circuit comprising a memory array of memory elements at an input supply voltage, wherein the input supply voltage changes over time;

determining, using a second circuit comprising a state-monitoring memory element of the memory array, if the input supply voltage drops below a threshold voltage at which the state-monitoring memory element operates, the state-monitoring memory element being representative of a voltage sensitivity of other memory elements of the memory array and the threshold voltage.

35. The method of claim 34, wherein said determining comprises providing a degraded input supply voltage to the state-monitoring memory element and to provide the input supply voltage to the other memory elements of the memory array, wherein the degraded input supply voltage is less than the input supply voltage.

36. The method of claim 34, wherein said determining comprises providing a degraded ground to the state-monitoring memory element.

37. The method of claim 34, wherein the state-monitoring memory element comprises a reduced ability to retain a logic state compared to one of the other memory elements, and wherein the state-monitoring memory element is configured to lose the logic state before the one memory element when the degraded input supply voltage drops below the threshold voltage.

38. The method of claim 34, wherein said determining comprises:

detecting a failure by the state-monitoring memory element to retain the logic state;

responsive to the detection, generating an indicator of the failure and issuing an interrupt signal to a system processor.

39. An apparatus, comprising:

means for extending a life of a battery used to power a first circuit comprising memory elements of a memory array, the memory array comprising a first memory element and a second memory element;

means for powering the first circuit directly with the at least one battery until a level of an input supply voltage of the battery substantially drops below a voltage threshold at which the first circuit operates; and

means for determining when the input supply voltage drops below the threshold voltage at which the first circuit operates using the first memory element, the first memory element being representative of a voltage sensitivity of the first circuit.

40. The apparatus of claim 39, further comprising:

means for detecting a failure in the first memory element; and

means for generating an indicator of failure responsive to detecting the failure by the first memory element earlier than a failure of the second memory element.