MULTI-MASTER BUS ARBITRATION AND RESOURCE CONTROL

• US 20120191891A1
• Filed: 12/15/2011
• Published: 07/26/2012
• Est. Priority Date: 01/21/2011
• Status: Active Grant

• Current Assignee: Numia Medical Technology, LLC
• Original Assignee: Numia Medical Technology, LLC
• Inventors: Allen, Duane E., Allen, James Jay
• Granted Patent: US 8,984,194 B2
• Time in Patent Office: Days
• US Class Current: 710/113
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

The present invention discloses an arbitration mechanism for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must he restricted, is applicable to any shared source in a computer or computer-controlled system. The present design delivers the following advantageous features. It provides localized arbitration to obtain resource access and localized self-management of resource mastery; eliminates resource seizure locally; it allows equal access to the share resource, encapsulate all four above features with the same circuit/protocol.

Claims

1. An apparatus for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must be restricted, in a computer or computer-controlled system, the apparatus comprising

an aggregation component capable of generating a biased signal from a request signal of a node of the plurality of node requesting access to the shared resource,

a reference signal, and

a comparator in which the reference signal is preset comparing the reference signal with the biased signal and generating a logic output signal.

2. The apparatus of claim 1, wherein the comparator is a voltage comparator.

3. The apparatus of claim 2 further comprising at least one resistor in series with the aggregation component, wherein the aggregation component comprising a plurality of parallel resistors.

4. The apparatus of claim 3, wherein the aggregation component further comprising a plurality of resistor controls correspondingly control each of the plurality of parallel resistors to connect to or disconnect to the aggregation component.

5. The apparatus of claim 2, wherein the voltage comparator is a dedicated voltage comparator.

6. The apparatus of claim 2, wherein the voltage comparator is an operational amplifier configured to function as a voltage comparator.

7. The apparatus of claim 1, wherein the comparator comprising a digital comparator or an analog signal comparator.

8. The apparatus of claim 7, wherein the digital comparator further comprising an analog to digital converter, converting the biased signal from the aggregation component to a digital value.

9. The apparatus of claim 2, wherein a TTL voltage level is utilized when the plurality of nodes are microprocessors, otherwise a PLC voltage level is utilized.

10. The apparatus of claim 2 further comprising a decision making logic capable of sending/remove the request signal, requesting access to the shared resource, of a node of the plurality of nodes with which the decision making logic associate to/from the aggregation component and receiving the logic output signal from the comparator interpreting the logic output signal as either “

access to the share resource granted”

or “

access to the share resource denied”

.

11. The apparatus of claim 10, wherein a two-wire system is applied.

12. The apparatus of claim 11, wherein the decision making logic is positioned within the computer system and communicating with each of the plurality of nodes that need access to the shared resource.

13. The apparatus of claim 10, wherein a single-wire system is applied.

14. The apparatus of claim 13, wherein a node of the plurality of node is a microcontroller.

15. The apparatus of claim 14, wherein the decision making logic is positioned within and communicating with each of the plurality of nodes that need use the shared resource.

16. The apparatus of claim 10, wherein the decision making logic is software capable of sending/remove the request signal to/from the aggregation component and receiving and interpreting the logic output signal from the comparator, or hardware sending/remove the request signal to/from the aggregation component and receiving and interpreting the logic output signal from the comparator.

17. The apparatus of claim 1, further comprising a backoff algorithm mechanism assigning a random wait time to a node of the plurality node requesting access to the shared resource when the shared resource is unavailable.

18. The apparatus of claim 10, further comprising a safety mechanism capable of preventing over-long occupation by a node of the plurality of nodes.

19. The apparatus of claim 18, wherein the safety mechanism is a maximum possession time monitor that starts to count time when a node of the plurality of node starts to use the shared resource.

20. The apparatus of claim 19, wherein when the maximum possession time monitor arbitrarily expires or a node of the plurality of nodes completes utilization of the shared resource, the maximum possession time monitor stops counting time and the decision making logic removes the request signal from the aggregation component.

21. The apparatus of claim 1, wherein the share resource is a communication bus.

22. The apparatus of claim of 15, wherein the comparator is either located in a silicon of microcontroller or external to the silicon.

23. A method for controlling access to a shared resource in a system with a plurality of nodes external to the shared resource the method comprising

providing an aggregation component capable of generating a biased signal from a request signal of a node of the plurality of nodes requesting access to the shared resource,

providing a preset reference signal, and

providing a comparator in which the reference signal is preset comparing the reference signal with the biased signal to generate a logic output signal.

24. The method of claim 23 further comprising providing a decision making logic capable of sending the request signal of a node of the plurality of nodes with which the decision making logic is associated to the aggregation component and receiving the logic output signal from the comparator interpreting the a logic output signal as either “

access to the share resource granted”

or “

access to the share resource denied”

.