Diode structures with controlled injection efficiency for fast switching

• US 20120193676A1
• Filed: 01/31/2011
• Published: 08/02/2012
• Est. Priority Date: 01/31/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Bobde, Madhur, Guan, Lingpeng, Bhalla, Anup, Lui, Sik, Naik, Harsh
• Granted Patent: US 8,933,506 B2
• Time in Patent Office: Days
• US Class Current: 257/140
• CPC Class Codes: H01L 29/7391 Gated diode structures

Abstract

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Claims

1. A semiconductor device disposed in a semiconductor substrate comprising:

a second semiconductor layer of a second conductivity type located at a top portion of said semiconductor substrate; and

a first semiconductor layer of a first conductivity type located below said second semiconductor layer;

wherein the first semiconductor layer further comprises an injection efficiency controlling buffer layer of the first conductivity type disposed immediately below said second semiconductor layer of the second conductivity type, said injection efficiency controlling buffer layer being located in a top portion of the first semiconductor layer,

wherein the first semiconductor layer further comprises a drift region of the first conductivity type located below the injection efficiency controlling buffer layer wherein the injection efficiency controlling buffer layer is more heavily doped than the drift layer such that the injection efficiency of said second semiconductor layer is controlled, and wherein the first semiconductor layer and the second semiconductor layer comprise two parts of a diode, one part being an anode and the other part being a cathode.

2. The semiconductor device according to claim 1, wherein the first semiconductor layer further comprises:

a bottom heavily doped region of the first conductivity type located at the bottom of the semiconductor substrate;

a soft recovery buffer layer of said first conductivity type disposed above said bottom heavily doped region and below said drift region, said soft recovery buffer layer having a lower doping concentration than the bottom heavily doped region and a higher doping concentration than the drift region.

3. The semiconductor device according to claim 1, further comprising:

a trench gate opened in said semiconductor substrate extending into said injection efficiency controlling buffer layer.

4. The semiconductor device according to claim 3, wherein:

the trench gate further comprises a gate electrode biased such that it charge compensates said injection efficiency controlling buffer layer.

5. The semiconductor device according to claim 4, wherein:

the trench gate further comprises a gate electrode electrically connected to the second semiconductor layer.

6. The semiconductor device according to claim 3, further comprising:

a breakdown voltage enhancement doped region of a second conductivity type located between adjacent portions of said second semiconductor layer, wherein the breakdown voltage enhancement doped region is electrically floating.

7. The semiconductor device according to claim 3, further comprising:

a plurality of breakdown voltage enhancement doped regions of a second conductivity type located between adjacent portions of said second semiconductor layer wherein the plurality of said plurality of breakdown voltage enhancement doped regions are electrically floating.

8. The semiconductor device according to claim 3, further comprising:

a plurality of said trench gates located between adjacent portions of said second semiconductor layer.

9. The semiconductor device according to claim 8, further comprising:

floating regions of the second conductivity type located between adjacent trench gates within said plurality of trench gates, said floating regions being electrically floating.

10. The semiconductor device according to claim 8, further comprising:

a metal layer disposed on top of said semiconductor substrate electrically connected to said second semiconductor layer and said trench gates; and

lightly doped regions located between adjacent trench gates within said plurality of trench gates such that contact between said metal layer and said lightly doped regions form a Schottky contact.

11. The semiconductor device according to claim 3, wherein:

said first semiconductor layer further comprises a heavily doped region of the first conductivity type at the bottom of said first semiconductor layer, said heavily doped region being disposed on a partial area on the bottom surface of said semiconductor substrate, such that another area on the bottom surface does not contain said heavily doped region.

12. The semiconductor device according to claim 3, wherein the first conductivity type is N-type and the second conductivity type is P-type.

13. The semiconductor device according to claim 3, wherein:

the first semiconductor layer and the second semiconductor layer form a vertical diode,

wherein the semiconductor substrate further comprises an insulated gate bipolar transistor (IGBT) such that said diode is integrated with said IGBT.

14. The semiconductor device according to claim 3, wherein the first semiconductor layer further comprises:

a bottom heavily doped region of the first conductivity type located at the bottom of the semiconductor substrate;

a soft recovery buffer layer of said first conductivity type disposed above said bottom heavily doped region and below said drift region, said soft recovery buffer layer having a lower doping concentration than the bottom heavily doped region and a higher doping concentration than the drift region.

15. The semiconductor device according to claim 5, further comprising:

a top metal layer electrically connected to the trench gate and to the second semiconductor layer; and

a bottom metal layer on the bottom of the first semiconductor layer.

16. A method for manufacturing a semiconductor device disposed in a semiconductor substrate comprising:

forming a first semiconductor layer of a first conductivity type in said semiconductor substrate; and

forming a second semiconductor layer of a second conductivity type at a top portion of said semiconductor substrate, over the first semiconductor layer,

wherein said forming a first semiconductor layer further comprises forming an injection efficiency controlling buffer layer of the first conductivity type immediately below said second semiconductor layer of the second conductivity type and forming a drift layer of the first conductivity type below the injection efficiency controlling buffer layer such that the injection efficiency controlling buffer layer is more heavily doped than the drift region to control an injection efficiency of said second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer comprise two parts of a diode, with one part being an anode and the other part being a cathode.

17. The method according to claim 16, further comprising:

forming a trench gate extending into said injection efficiency controlling buffer layer to charge compensate the injection efficiency controlling buffer layer.

18. The method according to claim 17, further comprising:

electrically connecting a gate electrode of said trench gate to the second semiconductor layer.

19. The method according to claim 17, further comprising:

forming a breakdown voltage enhancement doped region of the second conductivity type between adjacent portions of said second semiconductor layer to increase a breakdown voltage and to control the injection, wherein said breakdown voltage enhancement doped region is electrically floating.

20. The method according to claim 17, further comprising:

forming a plurality of breakdown voltage enhancement doped regions of the second conductivity type between adjacent portions of said second semiconductor layer to increase a breakdown voltage and to control the injection, wherein said plurality of breakdown voltage enhancement doped regions are electrically floating.

21. The method according to claim 17, further comprising:

forming a plurality of trench gates extending into said injection efficiency controlling buffer layer, between adjacent portions of said second semiconductor layer.

22. The method according to claim 21, further comprising:

forming floating regions of the second conductivity type between adjacent gate trenches within said plurality of gate trenches, wherein said floating regions are formed at the same time as said second semiconductor layer.

23. The method according to claim 21, further comprising:

forming a metal layer on top of said semiconductor substrate, said metal layer electrically connected to said second semiconductor layer and to said trench gates; and

forming lightly doped regions between adjacent gate trenches within said plurality of gate trenches such that said lightly doped regions form Schottky contact with the metal layer.