SEMICONDUCTOR DEVICE HAVING AN AIRBRIDGE AND METHOD OF FABRICATING THE SAME

• US 20120193795A1
• Filed: 01/31/2011
• Published: 08/02/2012
• Est. Priority Date: 01/31/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies Wireless IP Singapore Pte Limited (Broadcom, Inc.)
• Inventors: WHETTEN, Timothy J., RICHLING, Wayne P.
• Granted Patent: US 8,962,443 B2
• Time in Patent Office: Days
• US Class Current: 257/753
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 2224/4013 Connecting within a semiconductor or solid-state body, i.e. fly strap, bridge strap
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a device having an airbridge on a substrate includes forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer. The method further includes undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening, and forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer. The photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer is removed, which includes etching the photoresist layer through the break in the adhesion layer. An insulating layer is formed on at least the adhesion layer, enhancing adhesion of the insulating layer to the plated conductive layer.

Claims

1. A method of forming a device having an airbridge on a substrate, the method comprising:

forming a plated conductive layer of the airbridge over at least a photoresist layer on a portion of the substrate, the plated conductive layer defining a corresponding opening for exposing a portion of the photoresist layer;

undercutting the photoresist layer to form a gap in the photoresist layer beneath the plated conductive layer at the opening;

forming an adhesion layer on the plated conductive layer and the exposed portion of the photoresist layer, the adhesion layer having a break at the gap beneath the plated conductive layer;

removing the photoresist layer and a portion of the adhesion layer formed on the exposed portion of the photoresist layer, the removing comprising etching the photoresist layer through the break in the adhesion layer; and

forming an insulating layer on at least the adhesion layer, which enhances adhesion of the insulating layer to the plated conductive layer.

2. The method of claim 1, wherein the adhesion layer covers at least a portion of sidewalls of the opening in the plated conductive layer.

3. The method of claim 1, wherein the adhesion layer formed on the exposed portion of the photoresist layer is lifted off by the etching of the photoresist layer.

4. The method of claim 1, wherein undercutting the photoresist layer comprises applying oxygen plasma to the exposed portion of the photoresist layer.

5. The method of claim 1, wherein the plated conductive layer comprises gold, and the insulating layer comprises silicon nitride.

6. The method of claim 5, wherein the adhesion layer comprises titanium.

7. The method of claim 5, wherein the adhesion layer comprises tantalum.

8. The method of claim 5, wherein the adhesion layer comprises titanium oxide.

9. The method of claim 1, further comprising:

forming a conductive seed layer electrically connected to the substrate and the photoresist layer; and

forming the plated conductive layer on the conductive seed layer, the opening in the plated conductive layer initially exposing a portion of the conductive seed layer.

10. The method of claim 9, further comprising:

etching the exposed portion of the conductive seed layer to expose the exposed portion of the photoresist layer in the opening in the plated conductive layer before undercutting the photoresist layer to form the gap beneath the plated conductive layer.

11. The method of claim 10, wherein the conductive seed layer comprises plated gold.

12. The method of claim 11, further comprising:

forming a conductive lower layer electrically connected to the substrate and the photoresist layer; and

forming the conductive seed layer on the conductive lower layer,

wherein the conductive lower layer comprises titanium tungsten.

13. A method of forming an airbridge extending from a conductive area of a gallium arsenide (GaAs) semiconductor device, the method comprising:

applying a first photoresist layer on a substrate, with or without a device, and developing the first photoresist layer to form a first photoresist pattern;

applying a conductive lower layer on the first photoresist layer;

applying a conductive seed layer on the conductive lower layer;

applying a second photoresist layer on the conductive seed layer, and etching the second photoresist layer to form a second photoresist pattern;

applying a plated gold layer on the conductive seed layer using an electroplating process;

removing the second photoresist pattern to form an opening in the plated gold layer corresponding to the airbridge of the semiconductor device, the opening exposing a portion of the conductive seed layer;

removing the exposed portion of the conductive seed layer, exposing a portion of the first photoresist pattern within the opening in the plated gold layer;

partially etching the exposed portion of the first photoresist pattern using oxygen plasma, the partial etching undercutting the photoresist layer to form a gap between the plated gold layer and the first photoresist pattern at the opening in the plated gold layer;

applying an adhesion layer on the plated gold layer and the exposed portion of the first photoresist pattern, the adhesion layer having a break at the gap between the plated gold layer and the first photoresist pattern;

removing the first photoresist pattern using a solvent applied to the first photoresist pattern through the break in the adhesion layer, the solvent lifting off a portion of the adhesion layer on the exposed portion of the first photoresist pattern; and

applying an insulating layer on the adhesion layer to enhance adhesion of the insulating layer to the plated gold layer.

14. The method of claim 13, wherein the adhesion layer comprises one of titanium or tantalum.

15. The method of claim 14, wherein the adhesion layer covers at least a portion of side walls of the opening in the plated gold layer.

16. The method of claim 13, wherein removing the second photoresist pattern comprises a flood expose and develop process.

17. The method of claim 16, wherein the GaAs semiconductor device comprises one of a monolithic microwave integrated circuit (MMIC), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), an enhancement-mode pseudomorphic high electron mobility transistor (E-pHEMT), a heterojunction bipolar transistor (HBT).

18. A semiconductor device, comprising:

a device pattern formed on a semiconductor substrate;

a seed layer formed on the device pattern;

an airbridge formed on the seed layer, the airbridge comprising a plated conductive material and defining an opening exposing a portion of the device pattern;

an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge; and

an insulating layer formed on the adhesion layer, the adhesion layer enhancing adhesion of the insulating layer to the plated conductive material of the airbridge.

19. The device of claim 19, wherein the plated conductive material comprises gold and the insulating layer comprises silicon nitride.

20. The device of claim 20, wherein the adhesion layer comprises a conductive adhesion material.