Methods for managing alignment and latency in interference suppression

• US 20120195360A1
• Filed: 12/08/2011
• Published: 08/02/2012
• Est. Priority Date: 09/20/2002
• Status: Active Grant

• Current Assignee: III Holdings 1, LLC
• Original Assignee: Rambus Inc.
• Inventors: Graham, Greg, Meyer, David R., Jain, Prashant, Narayan, Anand P.
• Granted Patent: US 8,842,786 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: G01S 19/22 Multipath-related issues
• CPC Class Codes: G01S 5/10 Position of receiver fixed by co-ordinating a plurality of position lines defined by path-difference measurements , e.g. omega or decca systemsG01S5/12 takes precedence ; beacons and receivers cooperating therewith G01S1/306, G01S1/308
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/7097 Interference-related aspects
• CPC Class Codes: H04B 1/7105 Joint detection techniques, e.g. linear detectors
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 2001/70935 using a bank of matched fileters, e.g. Fast Hadamard Transform
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.

Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.

Claims

1. An interference cancelling receiver, comprising:

at least one symbol estimator configured to operate on a signal stream to produce one or more symbol estimates from a signal stream;

one or more interference estimators coupled to the at least one symbol estimator to produce one or more of interference estimates; and

an interference estimate combiner coupled to the said one or more interference estimators configured to align the one or more interference estimates to a received time boundary to produce a composite interference estimate.

2. The interference cancelling receiver in claim 1, wherein the at least one symbol estimator is configured to operate on Rake combined data.

3. The interference cancelling receiver in claim 1, wherein the at least one symbol estimator is configured to operate on Equalizer combined data.

4. The interference cancelling receiver in claim 1, wherein the signal stream comprises data selected from one of an original received signal, an interference cancelled signal, and a combination of an original received signal and an interference cancelled signal.

5. The interference cancelling receiver in claim 1, wherein the at least one symbol estimator operates sequentially on a sorted list of sources, sorted on the basis of their earliest arriving multipath.

7. The chipset recited in claim 5, wherein the said symbol estimator is configured to operate at a different clock speed than the analog to digital converter.

8. The chipset recited in claim 5, where the symbol estimator comprises a Fast Hadamard Transform.

6. A chipset for receiving a signal, comprising:

a front end configured for receiving a signal;

an analog to digital converter configured for sampling the signal at a sample rate that is greater than or equal to a chipping rate to produce sample-rate data;

a downsampler configured for converting sample rate data to a chipping rate to create chip-level data;

a symbol estimator configured for operating on chip level data to create symbol level data;

a post-processor configured to operate on symbol level data to produce modified symbol level data;

a respreader configured to apply a spreading code to the modified symbol level data to create chip level data; and

an interpolator configured to interpolate the chip level data to create sample level data.