ASYMMETRIC SEMICONDUCTOR MEMORY DEVICE HAVING ELECTRICALLY FLOATING BODY TRANSISTOR
First Claim
1. An asymmetric bi-stable semiconductor memory cell comprising:
- a floating body region having at least two stable charge levels indicative of a state of the memory cell;
a first region in electrical contact with said floating body region;
a second region in electrical contact with said floating body region and spaced apart from said first region; and
a gate positioned between said first and second regions, such that said first region is on a first side of said memory cell relative to said gate and said second region is on a second side of said memory cell relative to said gate;
wherein performance characteristics of said first side are different from performance characteristics of said second side.
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Abstract
Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.
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Citations
30 Claims
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1. An asymmetric bi-stable semiconductor memory cell comprising:
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a floating body region having at least two stable charge levels indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions, such that said first region is on a first side of said memory cell relative to said gate and said second region is on a second side of said memory cell relative to said gate; wherein performance characteristics of said first side are different from performance characteristics of said second side. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An asymmetric semiconductor memory cell comprising:
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a floating body region storing a charge or lack of charge indicative of a state of the memory cell; a first region in electrical contact with said floating body region; an electrode electrically connected to said floating body region, wherein said electrode forms a Schottky contact with the floating body region; and a gate positioned between said first region and said electrode. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor memory cell comprising:
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a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type;
said floating body region storing a charge or lack of charge indicative of a state of the memory cell;a first region having said first conductivity type and being in electrical contact with said floating body region; and a gate positioned above said floating body region. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. A memory array comprising:
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a plurality of asymmetric, bi-stable semiconductor memory cells, each said asymmetric, bi-stable memory cell comprising; a floating body region having at least two stable charge levels indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions, such that said first region is on a first side of said memory cell relative to said gate and said second region is on a second side of said memory cell relative to said gate, wherein performance characteristics of said first side are different from performance characteristics of said second side; a substrate; and a buried layer in said substrate, wherein said substrate is separated from said floating body region by said buried layer; at least two of said memory cells being commonly connected to at least one of; a word line terminal electrically connected to said gates, respectively, of said at least two memory cells; a bit line terminal electrically connected to said first regions, respectively, of said at least two memory cells; a source line terminal electrically connected to said second regions, respectively, of said at least two memory cells; a buried well terminal electrically connected to said buried layers, respectively, of said at least two memory cells;
ora substrate terminal electrically connected to said substrates, respectively, of said at least two memory cells. - View Dependent Claims (30)
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Specification