NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
First Claim
1. A non-volatile semiconductor storage device comprising:
- a memory string including a plurality of memory cells connected in series;
a first selection transistor having one end connected to one end of the memory string;
a first wiring having one end connected to the other end of the first selection transistor;
a second wiring connected to a gate of the first selection transistor; and
a control circuit configured to perform erase operation, the control circuit being configured to boost the first wiring to a first voltage and to boost the second wiring to a second voltage in the erase operation with keeping a first potential difference, the first potential difference being a potential difference for erasing data of the memory cells, and then starting boosting the first wiring from the first voltage.
4 Assignments
0 Petitions
Accused Products
Abstract
A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.
1 Citation
6 Claims
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1. A non-volatile semiconductor storage device comprising:
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a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor; and a control circuit configured to perform erase operation, the control circuit being configured to boost the first wiring to a first voltage and to boost the second wiring to a second voltage in the erase operation with keeping a first potential difference, the first potential difference being a potential difference for erasing data of the memory cells, and then starting boosting the first wiring from the first voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification