DENSE ARRAYS AND CHARGE STORAGE DEVICES

• US 20120223380A1
• Filed: 05/10/2012
• Published: 09/06/2012
• Est. Priority Date: 08/14/2000
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Lee, Thomas H., Subramanian, Vivek, Cleeves, James M., Walker, Andrew J., Petti, Christopher J., Kouznetzov, Igor G., Johnson, Mark G., Farmwald, Paul Michael, Herner, Brad
• Granted Patent: US 8,981,457 B2
• Time in Patent Office: Days
• US Class Current: 257/321
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5612 Multilevel memory cell with more than one floating gate
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1604 Amorphous materials
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42332 with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
• CPC Class Codes: H01L 29/42364 : characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/511 : with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 : the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 : the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 : the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66825 : with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 : with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7391 : Gated diode structures
• CPC Class Codes: H01L 29/78642 : Vertical transistors
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7889 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/792 : with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 : Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/861 : Diodes
• CPC Class Codes: H01L 29/8616 : Charge trapping diodes
• CPC Class Codes: H10B 20/00 : Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/60 : Peripheral circuit regions
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/10 : characterised by the top-view layout
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/23 : with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 43/27 : the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Claims

1. A memory device, comprising:

a substrate;

a first contact located over the substrate;

a vertical semiconductor pillar located over the first contact, a first end of the vertical semiconductor pillar contacting the first contact;

a second contact located over the vertical semiconductor pillar, wherein a second end of the vertical semiconductor pillar contacts the second contact;

a charge storage region located adjacent to a first side of the vertical semiconductor pillar;

a control gate located adjacent to the charge storage region;

a tunneling dielectric layer located between the first side of the vertical semiconductor pillar and charge storage region, and between the first contact and the control gate; and

a blocking dielectric layer located between the charge storage region and the control gate, and between the first contact and the control gate;

wherein the control gate is located entirely above the first contact.

2. The memory device of claim 1, wherein the vertical semiconductor pillar comprises a silicon pillar.

3. The memory device of claim 1, wherein the vertical semiconductor pillar comprises a first conductivity type semiconductor region in the first end, another first conductivity type region in the second end, and a second conductivity type region between the first conductivity type regions.

4. The memory device of claim 1, wherein the first conductivity type regions comprise source and drain regions and the second conductivity type region comprises a channel region.

5. The memory device of claim 1, wherein the first conductivity type regions comprise n-type regions and the second conductivity type region comprises a p-type region.

6. The memory device of claim 1, wherein the charge storage region comprises a floating gate.

7. The memory device of claim 1, wherein the charge storage region comprises a dielectric charge storage layer.

8. The memory device of claim 7, wherein the charge storage region comprises a silicon nitride layer and the tunneling and blocking dielectric layers comprise silicon oxide layers.

9. The memory device of claim 8, wherein a portion of the silicon nitride layer extends under the control gate between the tunneling and the blocking dielectric layers, and a bottom of the control gate is located on the blocking dielectric layer above the first contact.

10. The memory device of claim 1, wherein the first contact comprise tungsten, titanium silicide or tungsten silicide.

11. A method of making a memory device, comprising:

forming a first contact layer over a substrate;

forming a first semiconductor layer having a first conductivity type over the first contact layer;

forming a second semiconductor layer having a second conductivity type over the first semiconductor layer;

forming a third semiconductor layer having the first conductivity type over the second semiconductor layer;

patterning the first, second and third semiconductor layers to form semiconductor rails with gaps between the semiconductor rails;

forming a tunneling dielectric layer over sides of the semiconductor rails and over the first contact layer in the gaps;

forming a charge storage layer over the tunneling dielectric layer;

forming a blocking dielectric layer over the charge storage layer; and

forming a layer of control gate material over the blocking dielectric layer, wherein the layer of control gate material is located above the first contact layer.

12. The method of claim 11, further comprising patterning the semiconductor rails to form vertical semiconductor pillars and patterning the layer of control gate material to form control gates adjacent to a side of the vertical pillars.

13. The method of claim 12, wherein the vertical semiconductor pillars comprise silicon pillars.

14. The method of claim 12, wherein:

the vertical semiconductor pillars comprise a first conductivity type semiconductor region in a first end, another first conductivity type region in a second end, and a second conductivity type region between the first conductivity type regions; and

the first conductivity type regions comprise source and drain regions and the second conductivity type region comprises a channel region.

15. The method of claim 14, wherein the first conductivity type regions comprise n-type regions and the second conductivity type region comprises a p-type region.

16. The method of claim 12, wherein the charge storage layer comprises a floating gate.

17. The method of claim 12, wherein the charge storage layer comprises a dielectric charge storage layer.

18. The method of claim 17, wherein the charge storage layer comprises a silicon nitride layer and the tunneling and blocking dielectric layers comprise silicon oxide layers.

19. The method of claim 18, wherein a portion of the silicon nitride layer extends under the control gates between the tunneling and the blocking dielectric layers, and a bottom of the control gates is located on the blocking dielectric layer above the first contact.

20. The method of claim 12, further comprising forming a second contact over the vertical semiconductor pillars.