SYSTEM AND METHOD FOR PROVIDING ADAPTIVE MANUFACTURING DIAGNOSES IN A CIRCUIT BOARD ENVIRONMENT

• US 20120233104A1
• Filed: 03/07/2011
• Published: 09/13/2012
• Est. Priority Date: 03/07/2011
• Status: Active Grant

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Wang, Zhiyuan, Gu, Xinli, Wang, Zhanglei, Zhang, Zhaobo, Zong, Haoming
• Granted Patent: US 8,560,474 B2
• Time in Patent Office: Days
• US Class Current: 706/21
• CPC Class Codes: G06F 11/2257 using expert systems
• CPC Class Codes: G06N 3/042 Knowledge-based neural networks; Logical representations of neural networks

Abstract

An example method is provided and includes collecting inputs for a circuit board under test; evaluating historical repair records using a neuron network; providing repair actions for the circuit board based on the historical repair records; and providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, where the output is associated with a developed probability of successfully fixing an issue that was identified by the test. In more specific implementations, the inputs include fault syndromes and log files associated with the circuit board under test. Additionally, at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log. In yet other instances, particular outputs having higher probabilities are selected as the repair actions. The neuron network can be weighted using diagnosis knowledge weights.

Claims

1. A method, comprising:

collecting inputs for a circuit board under test;

evaluating historical repair records using a neuron network;

providing repair actions for the circuit board based on the historical repair records; and

providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, wherein the output is associated with a developed probability of successfully fixing an issue that was identified by the test.

2. The method of claim 1, wherein the inputs include fault syndromes and log files associated with the circuit board under test.

3. The method of claim 1, wherein at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log.

4. The method of claim 1, wherein particular outputs having higher probabilities are selected as the repair actions.

5. The method of claim 1, wherein the neuron network is weighted using diagnosis knowledge weights.

6. The method of claim 1, wherein the inputs include syndromes selected based on hardware designs and software designs related to the circuit board.

7. The method of claim 1, wherein a resultant of the repair actions is fed back into the neuron network.

8. Logic encoded in one or more tangible media that includes code for execution and when executed by a processor operable to perform operations comprising:

collecting inputs for a circuit board under test;

evaluating historical repair records using a neuron network;

providing repair actions for the circuit board based on the historical repair records; and

providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, wherein the output is associated with a developed probability of successfully fixing an issue that was identified by the test.

9. The logic of claim 8, wherein the inputs include fault syndromes and log files associated with the circuit board under test.

10. The logic of claim 8, wherein at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log.

11. The logic of claim 8, wherein particular outputs having higher probabilities are selected as the repair actions.

12. The logic of claim 8, wherein the neuron network is weighted using diagnosis knowledge weights.

13. The logic of claim 8, wherein the inputs include syndromes selected based on hardware designs and software designs related to the circuit board.

14. The logic of claim 8, wherein a resultant of the repair actions is fed back into the neuron network.

15. An apparatus, comprising:

a processor;

a memory element; and

a debugging tool, wherein the apparatus is configured for;

collecting inputs for a circuit board under test;

evaluating historical repair records using a neuron network;

providing repair actions for the circuit board based on the historical repair records; and

providing an output reflecting a particular component of the circuit board to be replaced or to be repaired, wherein the output is associated with a developed probability of successfully fixing an issue that was identified by the test.

16. The apparatus of claim 15, wherein the inputs include fault syndromes and log files associated with the circuit board under test.

17. The apparatus of claim 15, wherein at least one of the inputs of the neuron network is a syndrome vector extracted from a failure log.

18. The apparatus of claim 15, wherein particular outputs having higher probabilities are selected as the repair actions.

19. The apparatus of claim 15, wherein the neuron network is weighted using diagnosis knowledge weights.

20. The apparatus of claim 15, wherein the inputs include syndromes selected based on hardware designs and software designs related to the circuit board.