ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT

• US 20120242387A1
• Filed: 09/19/2011
• Published: 09/27/2012
• Est. Priority Date: 06/30/2005
• Status: Active Grant

• Current Assignee: Scott Pitkethly
• Original Assignee: Scott Pitkethly
• Inventors: Pitkethly, Scott
• Granted Patent: US 8,451,025 B2
• Time in Patent Office: Days
• US Class Current: 327/175
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Claims

1. A circuit comprising:

first circuitry configured to drive an output signal responsive to an input signal;

second circuitry configured to selectably adjust a duty cycle of said output signal, wherein a drive level of said first circuitry is independent of said duty cycle; and

third circuitry configured to produce a delayed version of said input signal, characterized by a delay that is greater than a transition time of said first circuitry less a delay of said second circuitry.

2. The circuit of claim 1 wherein said output signal is inverted relative to said input signal.

3. The circuit of claim 1 wherein said third circuitry is free of discrete components.

4. The circuit of claim 1 wherein said delayed version of said input signal is operable for changing a drive level of said output signal.

5. The circuit of claim 1 wherein a first state of said first circuitry comprises a high level drive circuit and a second state of said first circuitry comprises a substantially weaker level drive circuit.

6. The circuit of claim 5 wherein said substantially weaker level drive circuit comprises substantially no drive.

7. The circuit of claim 1 wherein said second state of said first circuitry comprises circuitry configured to implement a keeper mode.

8. The circuit of claim 1 wherein said input signal originates from a microprocessor clock signal.

9. The circuit of claim 1 wherein said output signal propagates through a maximum of three sequential devices.