WRITE DRIVER CIRCUIT FOR MRAM, MRAM AND LAYOUT STRUCTURE THEREOF

• US 20120257444A1
• Filed: 08/27/2011
• Published: 10/11/2012
• Est. Priority Date: 04/06/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: OH, Young Hoon
• Granted Patent: US 8,634,232 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A write driver circuit for a magnetic random access memory includes a memory cell array including a plurality of magnetic memory cells in which a pair of magnetic memory cells adjacent to each other in a direction of a bit line share a source line, and each magnetic memory cell is connected between the bit line and the source line. The write driver circuit includes a switching unit connected between a terminal for supplying a positive recording voltage and a terminal for supplying a negative recording voltage to selectively supply current generated by the positive recording voltage or the negative recording voltage to the bit line according to a write enable signal and a data signal.

Claims

1. A write driver circuit for a magnetic random access memory comprising a memory cell array comprising a plurality of magnetic memory cells, each of which comprises a pair of magnetic memory cells connected between a bit line and a source line, the write driver circuit comprising:

a switching unit configured to provide a positive recording voltage or a negative recording voltage to each magnetic memory cell to control the direction of current flow through the bit line connecting the magnetic memory cell according to a write enable signal and a data signal so as to influence the resistance state of the magnetic memory cell.

2. The write driver circuit according to claim 1, further comprising:

an input driving unit configured to determine whether to drive the switching unit in response to the write enable signal and the data signal.

3. The write driver circuit according to claim 2, wherein the input driving unit comprises:

a first driving section configured to output a first driving signal to the switching unit in response to the data signal and the write enable signal; and

a second driving section configured to output a second driving signal to the switching unit in response to the data signal and the write enable signal.

4. The write driver circuit according to claim 3, wherein the first driving section is configured to output a low level signal when the data signal and the write enable signal are at a low level, and the second driving section is configured to output a high level signal when the data signal and the write enable signal are at a high level.

5. A magnetic random access memory (MRAM) comprising one or more bit lines, word lines, and common source lines, the MRAM comprising:

a memory cell array comprising two or more magnetic memory cells, each of which is connected between a bit line and a common source line; and

a write driver circuit configured to control a current flow direction in the bit line of the magnetic memory cell, so as to affect the resistant state of the magnetic memory cell.

6. The magnetic random access memory according to claim 5, wherein two magnetic memory cells are connected to the common source line and wherein components in each of the two unit magnetic memory cells are connected in a mirror image of each other with respect to the common source line.

7. The magnetic random access memory according to claim 6, wherein the two magnetic memory cells comprise:

a first memory cell comprising a first magnetic tunnel junction and a first selection transistor connected in series between the bit line and the common source line; and

a second memory cell comprising a second selection transistor and a second magnetic tunnel junction connected in series between the common source line and the bit line.

8. The magnetic random access memory according to claim 5, wherein the write driver circuit is configured to provide a recording current to the bit line in order to record data in the magnetic memory cell, and a ground voltage is provided to the common source line in a data recording operation.

9. The magnetic random access memory according to claim 8, wherein the write driver circuit comprises:

a switching unit configured to provide either a positive recording voltage or a negative recording voltage to the bit line of the magnetic memory cell so as to selectively produce the current generated by the positive recording voltage or the negative recording voltage in the bit line according to a write enable signal and a data signal.

10. The magnetic random access memory according to claim 9, wherein the write driver circuit further comprises:

an input driving unit configured to determine whether to drive the switching unit to either the positive or negative recording voltage in response to the write enable signal and the data signal.

11. The magnetic random access memory according to claim 10, wherein the input driving unit comprises:

a first driving section configured to output a first driving signal to the switching unit in response to the data signal and the write enable signal; and

a second driving section configured to output a second driving signal to the switching unit in response to the data signal and the write enable signal.

12. The magnetic random access memory according to claim 11, wherein the first driving section is configured to output a low level signal when the data signal and the write enable signal are at a low level, and the second driving section is configured to output a high level signal when the data signal and the write enable signal are at a high level.

13. A magnetic random access memory, comprising:

a plurality of bit lines in a first direction;

a plurality of word lines in a second direction to the plurality of bit lines, wherein the first and second directions are not parallel;

a plurality of common source lines aligned in the second direction between a pair of the word lines; and

a memory cell array comprising two unit magnetic memory cells, each of which is connected between one of the bit lines and one of the common source lines and is driven by a signal applied to the word line connected to the memory cell,

wherein the two unit magnetic memory cells are formed to be adjacent to each other in the first direction and share the common source line.

14. The magnetic random access memory according to claim 13, wherein components of each of the two memory cells are connected between the bit line and the common source line but in a is manner resembling a mirror image of each other with respect to the common source line.

15. The magnetic random access memory according to claim 14, wherein the pair of memory cells sharing the common source line are formed on a same active area, and a dummy word line is further formed between adjacent active areas in a direction parallel to the word line.

16. The magnetic random access memory according to claim 14, wherein the components of each memory cell comprise a magnetic tunnel junction and a selection transistor connected in series.

17. The magnetic random access memory according to claim 16, wherein the resistance state of the magnetic tunnel junction is determined by the current flow direction through the magnetic tunnel junction between the bit line and the common source line.