SEMICONDUCTOR ELEMENT, MEMORY CIRCUIT, INTEGRATED CIRCUIT, AND DRIVING METHOD OF THE INTEGRATED CIRCUIT

• US 20120262995A1
• Filed: 04/09/2012
• Published: 10/18/2012
• Est. Priority Date: 04/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: SAKATA, Junichiro
• Granted Patent: US 8,878,174 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A novel semiconductor element contributing to an increase in circuit scale is provided. In the semiconductor element, two different electrical switches are formed using a single oxide semiconductor layer. For example, in the semiconductor element, formation of a channel (a current path) in the vicinity of a bottom surface (a first surface) of the oxide semiconductor layer and formation of a channel in the vicinity of a top surface (a second surface) of the oxide semiconductor layer are independently controlled. Therefore, the circuit area can be reduced as compared to the case two electrical switches are separately provided (for example, the case where two transistors are separately provided). That is, a circuit is formed using the semiconductor element, whereby an increase in the circuit area due to an increase in circuit scale can be suppressed.

Claims

1. A semiconductor element comprising:

an oxide semiconductor layer;

a first insulating layer in contact with a first surface of the oxide semiconductor layer;

a second insulating layer in contact with a second surface which is a back surface of the first surface of the oxide semiconductor layer;

a first conductive layer overlapping with the oxide semiconductor layer with the first insulating layer provided therebetween;

a second conductive layer overlapping with the oxide semiconductor layer with the second insulating layer provided therebetween;

a third conductive layer in electrical contact with the oxide semiconductor layer at one end of the first surface;

a fourth conductive layer in electrical contact with the oxide semiconductor layer at the other end of the first surface;

a fifth conductive layer in electrical contact with the oxide semiconductor layer at one end of the second surface; and

a sixth conductive layer in electrical contact with the oxide semiconductor layer at the other end of the second surface.

2. The semiconductor element according to claim 1,

wherein one end of the first conductive layer overlaps with one end of the third conductive layer with the first insulating layer provided therebetween and the other end of the first conductive layer overlaps with one end of the fourth conductive layer with the first insulating layer provided therebetween, and

wherein one end of the second conductive layer overlaps with one end of the fifth conductive layer with the second insulating layer provided therebetween and the other end of the second conductive layer overlaps with one end of the sixth conductive layer with the second insulating layer provided therebetween.

3. The semiconductor element according to claim 1,

wherein one end of the first conductive layer does not overlap with one end of the third conductive layer with the first insulating layer provided therebetween and the other end of the first conductive layer does not overlap with one end of the fourth conductive layer with the first insulating layer provided therebetween, and

wherein one end of the second conductive layer does not overlap with one end of the fifth conductive layer with the second insulating layer provided therebetween and the other end of the second conductive layer does not overlap with one end of the sixth conductive layer with the second insulating layer provided therebetween.

4. The semiconductor element according to claim 1, wherein the oxide semiconductor layer includes a first oxide semiconductor region having the first surface, a second oxide semiconductor region having the second surface, and an oxide insulator region interposed between the first oxide semiconductor region and the second oxide semiconductor region.

5. The semiconductor element according to claim 1, wherein the first conductive layer is closer to the third conductive layer and the fourth conductive layer than the second conductive layer is, and the second conductive layer is closer to the fifth conductive layer and the sixth conductive layer than the first conductive layer is.

6. A memory circuit comprising:

the semiconductor element according to claim 1,

a first memory element which holds data at a node electrically connected to the fourth conductive layer of the semiconductor element, and

a second memory element which holds data at a node electrically connected to the sixth conductive layer of the semiconductor element.

7. An integrated circuit comprising:

the memory circuit according to claim 6;

a first flip-flop electrically connected to the third conductive layer; and

a second flip-flop electrically connected to the fifth conductive layer.

8. The integrated circuit according to claim 7,

wherein the semiconductor element is provided in a region overlapping with the first flip-flop or the second flip-flop, and

wherein the first flip-flop and the second flip-flop include a transistor whose channel is formed in a polycrystalline silicon layer or a single crystal silicon layer.

9. A method for driving the integrated circuit according to claim 8, comprising the steps of:

transmitting data held in the first flip-flop and data held in the second flip-flop to the first memory element and the second memory element, respectively, before a period in which the supply of a power supply voltage to the first flip-flop and the second flip-flop is stopped;

holding the data in the first memory element and the data in the second memory element during the period; and

transmitting the data held in the first memory element to the first flip-flop, so that the data of the first flip-flop is restored and transmitting the data held in the second memory element to the second flip-flop, so that the data of the second flip-flop is restored, after the period.

10. The method for driving the integrated circuit according to claim 9,

wherein transmission of the data from the first flip-flop to the first memory element and transmission of the data from the second flip-flop to the second memory element are performed at the same time before the period.

11. The method for driving the integrated circuit according to claim 9,

wherein transmission of the data from the first memory element to the first flip-flop and transmission of the data from the second memory element to the second flip-flop are performed at the same time after the period.

12. A semiconductor element comprising:

an oxide semiconductor layer;

a first gate insulating layer and a second gate insulating layer;

a first gate and a second gate;

a first source and a second source; and

a first drain and a second drain;

wherein an electric field generated in the vicinity of a first surface of the oxide semiconductor layer with the first gate insulating layer provided between the first gate and the oxide semiconductor layer is controlled in accordance with a voltage between the first gate and the first source, whereby a channel which lies between the first source and the first drain is formed in the oxide semiconductor layer; and

wherein an electric field generated in the vicinity of a second surface which is a back surface of the first surface of the oxide semiconductor layer with the second gate insulating layer provided between the second gate and the oxide semiconductor layer is controlled in accordance with a voltage between the second gate and the second source, whereby a channel which lies between the second source and the second drain is formed in the oxide semiconductor layer.

13. The semiconductor element according to claim 12, wherein a region where the channel which lies between the first source and the first drain overlaps with the channel between the second source and the second drain is provided.

14. The semiconductor element according to claim 12, wherein the oxide semiconductor layer includes a first oxide semiconductor region having the first surface, a second oxide semiconductor region having the second surface, and an oxide insulator region interposed between the first oxide semiconductor region and the second oxide semiconductor region.

15. The semiconductor element according to claim 12, wherein the first gate is closer to the first source and the first drain than the second gate is, and the second gate is closer to the second source and the second drain than the first gate is.

16. A memory circuit comprising:

the semiconductor element according to claim 12,

a first memory element which holds data at a node electrically connected to one of the first source and the first drain of the semiconductor element; and

a second memory element which holds data at a node electrically connected to one of the second source and the second drain of the semiconductor element.

17. An integrated circuit comprising:

the memory circuit according to claim 16;

a first flip-flop electrically connected to the other of the first source and the first drain; and

a second flip-flop electrically connected to the other of the second source and the second drain.

18. The integrated circuit according to claim 17,

wherein the semiconductor element is provided in a region overlapping with the first flip-flop or the second flip-flop, and

wherein the first flip-flop and the second flip-flop include a transistor whose channel is formed in a polycrystalline silicon layer or a single crystal silicon layer.

19. A method for driving the integrated circuit according to claim 17, comprising the steps of:

transmitting data held in the first flip-flop and data held in the second flip-flop to the first memory element and the second memory element, respectively, before a period in which the supply of a power supply voltage to the first flip-flop and the second flip-flop is stopped;

holding the data in the first memory element and the data in the second memory element during the period; and

transmitting the data held in the first memory element to the first flip-flop, so that the data of the first flip-flop is restored and transmitting the data held in the second memory element to the second flip-flop, so that the data of the second flip-flop is restored, after the period.

20. The method for driving the integrated circuit according to claim 19,

wherein transmission of the data from the first flip-flop to the first memory element and transmission of the data from the second flip-flop to the second memory element are performed at the same time before the period.

21. The method for driving the integrated circuit according to claim 19,

wherein transmission of the data from the first memory element to the first flip-flop and transmission of the data from the second memory element to the second flip-flop are performed at the same time after the period.

22. A semiconductor element comprising:

an oxide semiconductor layer;

a first pair of electrodes in electrical contact with the oxide semiconductor layer, wherein a first channel is formed in the oxide semiconductor layer between the first pair of electrodes;

a second pair of electrodes in electrical contact with the oxide semiconductor layer, wherein a second channel is formed in the oxide semiconductor layer between the second pair of electrodes;

a first gate insulating layer adjacent to the oxide semiconductor layer; and

a first gate electrode adjacent to the oxide semiconductor layer with the first gate insulating layer interposed therebetween,

wherein the first channel and the second channel overlap each other at least partly.

23. The semiconductor element according to claim 22, further comprising:

a second gate insulating layer adjacent to the oxide semiconductor layer;

a second gate electrode adjacent to the oxide semiconductor layer with the second gate insulating layer interposed therebetween,

wherein the oxide semiconductor layer is located between the first gate insulating layer and the second gate insulating layer.