PHASE CHANGE MEMORY CYCLE TIMER AND METHOD
First Claim
1. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase change memory (PCM) cycle timer, wherein said HDL design structure comprises:
- at least one reference phase change element (PCE); and
a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE.
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Accused Products
Abstract
A phase change memory (PCM) cycle timer and associated method are disclosed. A system includes at least one reference phase change element (PCE). The system also includes a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE throughout a settling time of the at least one reference PCE.
4 Citations
20 Claims
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1. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase change memory (PCM) cycle timer, wherein said HDL design structure comprises:
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at least one reference phase change element (PCE); and a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method in a computer-aided design system for generating a functional design model of a phase change memory (PCM) cycle timer, said method comprising:
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generating a functional representation of at least one reference phase change element (PCE); and generating a functional representation of a circuit that performs a write operation on the at least one reference PCE and substantially immediately thereafter continuously senses and returns a value of a resistance of the at least one reference PCE. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A hardware description language (HDL) design structure encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a phase change memory (PCM) cycle timer, wherein said HDL design structure comprises:
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a memory controller associated with a phase change memory (PCM) array; and a cycle timer comprising at least one reference phase change element (PCE), wherein a write command from the memory controller to a portion of the PCM array triggers the cycle timer to fill charge traps of the at least one reference PCE and thereafter continuously sense and return a value of a resistance of the at least one reference PCE. - View Dependent Claims (19, 20)
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Specification