SEMICONDUCTOR DEVICE

• US 20120267696A1
• Filed: 04/13/2012
• Published: 10/25/2012
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ISOBE, Atsuo, SASAKI, Toshinari
• Granted Patent: US 8,809,854 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.

Claims

1. A semiconductor device comprising:

a trench provided in an insulating layer, wherein the trench includes a lower end corner portion having a curved shape;

an oxide semiconductor film in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench;

a gate insulating layer over the oxide semiconductor film; and

a gate electrode layer over the gate insulating layer,

wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm

2. The semiconductor device according to claim 1, wherein a surface of the insulating layer in the lower end corner portion having the curved shape has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm

3. The semiconductor device according to claim 1, wherein a surface of the insulating layer in contact with the oxide semiconductor film has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm

4. The semiconductor device according to claim 1, further comprising a source electrode and a drain electrode in contact with the oxide semiconductor film.

5. The semiconductor device according to claim 4, wherein the source electrode and the drain electrode do not overlap with the gate electrode layer.

6. The semiconductor device according to claim 1, wherein the trench is filled with the gate electrode layer.

7. A memory device comprising the semiconductor device according to claim 1.

8. A semiconductor device comprising:

a trench provided in an insulating layer, wherein the trench includes a lower end corner portion having a curved shape;

an oxide semiconductor film in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor film;

a gate insulating layer over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and

a gate electrode layer over the gate insulating layer,

wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and

wherein the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor film at least over the lower end corner portion.

9. The semiconductor device according to claim 8, wherein a surface of the insulating layer in the lower end corner portion having the curved shape has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm

10. The semiconductor device according to according to claim 8, wherein a surface of the insulating layer in contact with the oxide semiconductor film has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm

11. The semiconductor device according to claim 8, wherein the source electrode layer and the drain electrode layer do not overlap with the gate electrode layer.

12. The semiconductor device according to claim 8, wherein the trench is filled with the gate electrode layer.

13. A memory device comprising the semiconductor device according to claim 8.

14. A semiconductor device comprising:

a first transistor comprising;

a channel formation region including a semiconductor material; and

a first gate electrode overlapping with the channel formation region,

an insulating layer covering the first transistor, wherein part of the first gate electrode is exposed without being covered with the insulating layer,

a second transistor comprising;

a trench provided in the insulating layer, wherein the trench includes a lower end corner portion having a curved shape;

an oxide semiconductor film in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench;

a source electrode layer and a drain electrode layer in contact with the oxide semiconductor film;

a gate insulating layer over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and

a second gate electrode layer over the gate insulating layer,

wherein the lower end corner portion has a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and

wherein one of the source electrode layer and the drain electrode layer of the second transistor is in direct contact with the part of the first gate electrode.

15. The semiconductor device according to claim 14, further comprising a capacitor, wherein the capacitor comprises one of the source electrode layer and the drain electrode layer, the gate insulating layer, and an electrode provided over the gate insulating layer.

16. The semiconductor device according to claim 14, wherein the oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor film at least over the lower end corner portion.

17. The semiconductor device according to claim 14, wherein a surface of the insulating layer in the lower end corner portion having the curved shape has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm

18. The semiconductor device according to according to claim 14, wherein a surface of the insulating layer in contact with the oxide semiconductor film has an average surface roughness of more than or equal to 0.1 nm and less than 0.5 nm

19. The semiconductor device according to claim 14, wherein the source electrode layer and the drain electrode layer do not overlap with the second gate electrode layer.

20. The semiconductor device according to claim 14, wherein the trench is filled with the second gate electrode layer.