COMPARATOR WITH ADAPTIVE TIMING

• US 20120268185A1
• Filed: 04/22/2011
• Published: 10/25/2012
• Est. Priority Date: 04/22/2011
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: KAPUSTA, Ronald
• Granted Patent: US 8,487,659 B2
• Time in Patent Office: Days
• US Class Current: 327/288
• CPC Class Codes: H03K 2005/00065 by current control, e.g. by parallel current control transistors
• CPC Class Codes: H03M 1/0617 characterised by the use of methods or means not specific to a particular type of detrimental influence
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/46 with digital/analogue converter for supplying reference values to converter

Abstract

An adaptive delay device that provides a delay to a signal based on circuit conditions such as temperature, supply voltage values and/or fabrication processes. The adaptive delay device may respond to circuit conditions by charging a capacitive device to a threshold voltage. A comparator may incorporate the adaptive delay device to provide adaptive timing for the comparator functions thereby attaining improved noise performance and/or reduce power consumption.

Claims

1. An adaptive delay device, comprising:

an inverter for receiving an input signal;

a capacitor having a first terminal coupled to an output of the inverter and a second terminal coupled to a first voltage supply; and

a transistor having an input terminal coupled to the inverter output, a source coupled to a second voltage supply and a drain coupled to an output terminal.

2. The adaptive delay device of claim 1, comprising:

a bias current source that provides a current to the inverter.

3. The adaptive delay device of claim 1, comprising:

a resistor coupled to the inverter.

4. The adaptive delay device of claim 1, comprising:

a proportional-to-absolute temperature current source that provides a variable current based on a temperature of circuit components to the inverter.

5. The adaptive delay device of claim 1, comprising:

a current source to bias the transistor.

6. The adaptive delay device of claim 1, wherein the capacitor and transistor react to circuit conditions that include at least one of variations in supply voltage and variations in fabrication processes of circuit components forming the adaptive delay device by adapting a delay to an output signal.

7. The adaptive delay device of claim 6, wherein the delay to the output signal is adapted by increasing or decreasing the delay to oppose the PVT effects of other circuit components adjacent to the adaptive delay device.

8. The adaptive delay device of claim 1, wherein the capacitor and transistor react to circuit conditions include at least one of variations in supply voltage, variations in fabrication processes and temperature of the circuit components forming the adaptive delay device by adapting a delay to an output signal.

9. The adaptive delay device of claim 8, wherein the delay to the output signal is adapted by increasing or decreasing the delay to oppose the PVT effects of other circuit components adjacent to the adaptive delay device.

10. A dynamically adaptive delay device, comprising:

an inverter for receiving an input signal;

a capacitive element;

a current source for selectively delivering a current through the inverter to the capacitive element, wherein the magnitude of the current remains constant in response to varying circuit conditions; and

a transistor responsive to a voltage created on the capacitor in response to the current delivered by the current source.

11. The delay device of claim 10, wherein the capacitor and the transistor react to circuit conditions includes at least one of variation in supply voltage and variation in fabrication processes by adapting a delay of a signal to be output from an output terminal coupled to the transistor.

12. The delay device of claim 11, wherein the delay to the output signal is adapted by increasing or decreasing the delay to oppose the PVT effects of other circuit components adjacent to the delay device.

13. The delay device of claim 10, wherein the capacitor and the transistor react to circuit conditions includes at least one of variations in supply voltage, variation in circuit temperature and variation in fabrication processes by delaying output of a signal on an output terminal coupled to the transistor.

14. The adaptive delay device of claim 13, wherein the delay to the output signal is adapted by increasing or decreasing the delay to oppose the PVT effects of other circuit components adjacent to the delay device.

15. The delay device of claim 10, wherein a pair of a plurality of intermediate switches are configured as an inverter, and an output of the inverter is connected to a first terminal of a capacitor and to a control input of another switch of the plurality of intermediate switches.

16. The delay device of claim 10, wherein the current is proportional to the temperature of circuit components of the delay device.

17. The delay device of claim 10, wherein the current source comprises:

a first pair of transistors configured as a current mirror;

a second pair of transistors with commonly connected control inputs connected to a drain terminal of one transistor of the first pair of transistors; and

a single transistor with a control input connected to a terminal of a resistive element.

18. A comparator, comprising:

a preamplifier responsive to a first control signal;

a latch responsive to a second control signal; and

a delay element, having an input for the first control signal and an output for the second control signal, the delay element having a circuit structure to adaptively increase or decrease delay propagation of the first control signal in a manner that counteracts PVT effects present in other components of the comparator.

19. The comparator of claim 18, wherein the adaptive delay device further comprises:

a capacitive element for supplying a threshold voltage to a control input of an output switch; and

an intermediate switch for selectively delivering a current to the capacitive element, wherein the capacitive element charges to a threshold voltage that actuates the output switch which changes an output signal, wherein a time required to charge the capacitive element to the threshold voltage varies in response to circuit conditions of the comparator.

20. The comparator of claim 19, wherein a current source provides the current to the capacitive element, and the current is proportional to the temperature of circuit components of the comparator.

21. The comparator of claim 20, wherein the current source comprises:

a first pair of transistors configured as a current mirror;

a second pair of transistors with commonly connected control inputs connected to a drain terminal of one transistor of the first pair of transistors; and

a single transistor with a control input connected to a terminal of a resistive element.

22. A successive approximation register analog-to-digital converter on an integrated circuit chip configured with a plurality of on-chip circuit components, comprising:

a comparator for determining whether an input signal is representative of a digital high or low signal; and

an adaptive delay device having an input for receiving a control signal and an output connected to the comparator, wherein the adaptive delay device is configured to respond inversely to the response of other circuit components forming the successive approximation register analog-to-digital converter, and output the control signal to the comparator based on the inverse response of the adaptive delay device.

23. The successive approximation register analog-to-digital converter of claim 22, wherein the adaptive delay device further comprises:

a capacitive element for supplying a threshold voltage to a control input of an output switch; and

an intermediate switch for selectively delivering a current to the capacitive element, wherein the capacitive element charges to a threshold voltage that actuates the output switch which changes an output signal, wherein the time required to charge the capacitive element to the threshold voltage is responsive to circuit conditions of the converter.

24. The successive approximation register analog-to-digital converter of claim 23, wherein the current is proportional to the temperature of circuit components of the converter, and provided by a current source.

25. The successive approximation register analog-to-digital converter of claim 24, wherein the current source comprises:

a first pair of transistors configured as a current mirror;

a second pair of transistors with commonly connected control inputs connected to a drain terminal of one transistor of the first pair of transistors; and

a single transistor with a control input connected to a terminal of a resistive element.

26. A method of controlling PVT effects in a circuit system, comprising:

responsive to a state change in an input signal, charging a capacitive element with reference to a first supply voltage; and

when the capacitive element'"'"'s output voltage reaches a voltage threshold, generating an output voltage;

wherein the method is performed in an integrated circuit, and delays between the state change of the input signal and the generated output voltage vary inversely in response to PVT effects on other components of the integrated circuit.

27. The method of claim 26, wherein the voltage threshold is set by determining when an output voltage of the capacitive element is within a voltage threshold of a second supply voltage, opposite from the first supply voltage.

28. The method of claim 26, wherein the generated output voltage is a same voltage as the input signal.