METHOD OF FABRICATING A DUMMY GATE STRUCTURE IN A GATE LAST PROCESS

• US 20120270379A1
• Filed: 06/29/2012
• Published: 10/25/2012
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lai, Su-Chen, Wu, Ming-Yuan, Thei, Kong-Beng, Chuang, Harry Hak-Lay, Yeh, Chiung-Han, Chang, Hong-Dyi, Cheng, Kuo Cheng, Wu, Chien-Hung, Lee, Tzung-Chi
• Granted Patent: US 8,530,326 B2
• Time in Patent Office: Days
• US Class Current: 438/401
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind

Abstract

A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.

Claims

1. A method of semiconductor device fabrication, comprising:

forming a plurality of gate structures in a first portion of a substrate;

forming a first metal gate structure in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region; and

forming a plurality of dummy gate structures in the second portion of the substrate, wherein the plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region, wherein the plurality of dummy structures have a top surface that is substantially planar with a top surface of the plurality of gate structures, and wherein the first polishing stopper covers at least 5% of a pattern density of the second portion of the substrate.

2. The method of claim 1, further comprising:

forming a monitor pad in a third portion of the substrate, wherein the monitor pad includes a plurality of layers disposed in a stack, wherein the monitor pad includes at least two layers that have a same composition as at least two layers of the plurality of gate structures in the first portion of a substrate.

3. The method of claim 2, wherein the plurality of gate structures in the first portion each include a high-k dielectric layer and a metal layer, and wherein the at least two layers of the monitor pad include the high-k dielectric layer and the metal layer.

4. The method of claim 2, further comprising:

forming a second plurality of dummy structures disposed adjacent at least two sides of the monitor pad, wherein the second plurality of dummy structures is formed concurrently with the plurality of gate structures.

5. The method of claim 1, further comprising:

forming an alignment mark in a third portion of the substrate; and

using the alignment mark to align a photomask and the semiconductor substrate during a photolithography process.

6. The method of claim 5, further comprising:

forming a second plurality of dummy structures disposed adjacent at least two sides of the alignment mark, wherein the second plurality of dummy structures if formed concurrently with the plurality of gate structures.

7. The method of claim 1, further comprising:

forming an active region in the second portion of the substrate, wherein the first metal gate structure is formed on the active region; and

forming the isolation region immediately adjacent the active region.

8. The method of claim 7, further comprising:

forming dummy active regions in the second portion of the substrate concurrently with forming the active region, wherein the plurality of dummy structures are formed on the dummy active regions.

9. The method of claim 1, wherein the forming the plurality of dummy structures includes forming a polysilicon layer.

10. The method of claim 1, wherein the second portion of the substrate has an area that is at least 20 mm by 20 mm.

11. The method of claim 1, wherein the forming the plurality of gate structures in the first portion of the substrate includes forming a dummy polysilicon layer and wherein the forming the plurality of dummy gate structures including forming a polysilicon layer concurrently with the dummy polysilicon layer.

12. The method of claim 1, further comprising:

forming an interlayer dielectric (ILD) on the plurality of gate structures and the plurality of dummy gate structures;

performing a chemical mechanical polish (CMP) process on the ILD; and

using a top surface of the plurality of dummy gate structures as a stopper for the CMP process.

13. A method of fabricating a semiconductor device, comprising:

forming an isolation region in a semiconductor substrate, thereby defining a first area and a second area, the first and second areas being interposed by the isolation region;

forming a plurality of transistors formed in the first area, wherein the forming the plurality of transistors includes;

forming a first plurality of dummy polysilicon gate structures;

removing a layer of each of the first plurality of dummy polysilicon gate structures to provide trenches; and

forming metal gate electrodes in the trenches;

forming a device element formed in the second area, wherein the device element is one of a MOS device, a BJT device, a diode, and a resistor; and

forming a polishing stopper in the second area, wherein forming the polishing stopper includes forming a second plurality of dummy polysilicon gate structures in a ring encircling the device element, wherein the second plurality of dummy polysilicon gate structures are formed concurrently with forming the first dummy polysilicon gate structures of the plurality of transistors.

14. The method of claim 13, further comprising:

forming a monitor pad on the semiconductor substrate, wherein the monitor pad includes a stack of material including a first dielectric layer, a first conductive layer, and a second dielectric layer; and

forming a polishing stopper adjacent the monitor pad, the polishing stopper formed over the substrate.

15. The method of claim 14, wherein the forming the monitor pad is performed concurrently with forming the dummy polysilicon gate structure.

16. A method of semiconductor device fabrication, comprising:

forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height;

forming a first metal gate structure in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region; and

forming a first plurality of dummy gate structures in the second portion of the substrate, wherein the first plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region, wherein first the plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures;

forming an alignment mark in a third portion of the substrate;

forming a second plurality of dummy gate structures in the third portion of the substrate, wherein the second plurality of dummy gate structures are formed concurrently with the first plurality of dummy gate structures; and

using the alignment mark to align a photomask and the semiconductor substrate during a photolithography process.

17. The method of claim 16, wherein the second plurality of dummy gate structures are formed inside a feature of the alignment mark.

18. The method of claim 17, wherein the feature of the alignment mark is an overlay box.

19. The method of claim 16, wherein the second plurality of dummy gate structures covers at least 5% of a pattern density of the third portion of the substrate.

20. The method of claim 16, wherein the first plurality of dummy gate structures covers at least 5% of a pattern density of the second portion of the substrate.