Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

• US 20120273959A1
• Filed: 04/30/2011
• Published: 11/01/2012
• Est. Priority Date: 04/30/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Park, DongSam, Lee, YongDuk
• Granted Patent: US 9,087,701 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2518 : being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/1035 : the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Claims

1. A method of making a semiconductor device, comprising:

providing a substrate;

forming a first conductive layer over a surface of the substrate;

forming a plurality of cavities in the substrate to expose the first conductive layer;

mounting a first semiconductor die having conductive through silicon vias (TSV) into the cavities of the substrate;

forming a first insulating layer over the substrate and first semiconductor die extending into the cavities to embed the first semiconductor die within the substrate;

removing a portion of the first insulating layer to expose the conductive TSV;

forming a second conductive layer over the conductive TSV;

removing a portion of the first conductive layer to form electrically common or electrically isolated conductive segments of the first conductive layer; and

forming a second insulating layer over the substrate and conductive segments of the first conductive layer.

2. The method of claim 1, further including:

removing a portion of the second insulating layer to expose the conductive segments of the first conductive layer; and

forming a plurality of bumps over the conductive segments of the first conductive layer.

3. The method of claim 1, further including singulating the substrate to separate the first semiconductor die.

4. The method of claim 1, further including conformally applying the second conductive layer to follow a contour of the first insulating layer into the removed portion of the first insulating layer.

5. The method of claim 1, further including mounting a second semiconductor die over the substrate electrically connected to the second conductive layer.

6. The method of claim 5, further including:

forming non-collapsible conductive posts over contact pads of the second semiconductor die; and

forming fusible bumps over the non-collapsible conductive posts prior to mounting a second semiconductor die over the first substrate.

7. A method of making a semiconductor device, comprising:

providing a first substrate with a first conductive layer and a plurality of cavities exposing the first conductive layer;

mounting a first semiconductor die with conductive vias into the cavities of the first substrate;

forming a first insulating layer over the first substrate and first semiconductor die;

removing a portion of the first insulating layer to expose the conductive vias;

forming a second conductive layer over the conductive vias;

removing a portion of the first conductive layer to form electrically common or electrically isolated conductive segments of the first conductive layer; and

forming a second insulating layer over the first substrate and conductive segments of the first conductive layer.

8. The method of claim 7, wherein the first insulating layer extends into the cavities to embed the first semiconductor die within the first substrate.

9. The method of claim 7, further including:

removing a portion of the second insulating layer to expose the conductive segments of the first conductive layer; and

forming an interconnect structure over the conductive segments of the first conductive layer.

10. The method of claim 7, further including conformally applying the second conductive layer to follow a contour of the first insulating layer into the removed portion of the first insulating layer.

11. The method of claim 7, further including mounting a second semiconductor die over the first substrate electrically connected to the second conductive layer.

12. The method of claim 11, further including forming an interconnect structure over contact pads of the second semiconductor die prior to mounting a second semiconductor die over the first substrate.

13. The method of claim 7, further including:

providing a second substrate;

mounting a second semiconductor die to the first substrate;

mounting a third semiconductor die to the second semiconductor die; and

mounting the second substrate to the second conductive layer.

14. A method of making a semiconductor device, comprising:

providing a first substrate with a first conductive layer and a plurality of cavities exposing the first conductive layer;

mounting a first semiconductor die with conductive vias into the cavities of the first substrate;

forming a first insulating layer over the first substrate and first semiconductor die;

forming a second conductive layer over the first insulating layer electrically connected to the conductive vias; and

removing a portion of the first conductive layer to form electrically common or electrically isolated conductive segments of the first conductive layer.

15. The method of claim 14, further including forming a second insulating layer over the first substrate and conductive segments of the first conductive layer.

16. The method of claim 14, wherein the first insulating layer extends into the cavities to embed the first semiconductor die within the first substrate.

17. The method of claim 14, further including:

removing a portion of the second insulating layer to expose the conductive segments of the first conductive layer; and

forming an interconnect structure over the conductive segments of the first conductive layer.

18. The method of claim 14, further including conformally applying the second conductive layer to follow a contour of the first insulating layer.

19. The method of claim 14, further including mounting a second semiconductor die over the first substrate electrically connected to the second conductive layer.

20. The method of claim 14, further including:

providing a second substrate;

mounting a second semiconductor die to the first substrate;

mounting a third semiconductor die to the second semiconductor die; and

mounting the second substrate to the second conductive layer.

21. A semiconductor device, comprising:

a first substrate with a first conductive layer and a plurality of cavities exposing the first conductive layer;

a first semiconductor die with conductive vias mounted into the cavities of the first substrate;

a first insulating layer formed over the first substrate and first semiconductor die; and

a second conductive layer formed over the first insulating layer and electrically connected to the conductive vias, wherein a portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer.

22. The semiconductor device of claim 21, further including a second insulating layer formed over the first substrate and conductive segments of the first conductive layer.

23. The semiconductor device of claim 21, wherein the first insulating layer extends into the cavities to embed the first semiconductor die within the first substrate.

24. The semiconductor device of claim 21, further including a second semiconductor die mounted to the first substrate and electrically connected to the second conductive layer.

25. The semiconductor device of claim 21, further including:

a second substrate;

a second semiconductor die mounted to the first substrate;

a third semiconductor die mounted to the second semiconductor die; and

the second substrate mounted to the second conductive layer.