CONTROLLING NANOSTORE OPERATION BASED ON MONITORED PERFORMANCE

• US 20120278650A1
• Filed: 04/29/2011
• Published: 11/01/2012
• Est. Priority Date: 04/29/2011
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Muralimanohar, Naveen, Ranganathan, Parthasarathy, Chang, Jichuan
• Granted Patent: US 8,661,298 B2
• Time in Patent Office: Days
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/2038 with a single idle spare processing component
• CPC Class Codes: G06F 11/34 Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Abstract

Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.

Claims

1. A method comprising:

monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic; and

controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.

2. A method as defined in claim 1 wherein monitoring performance of the nanostore comprises monitoring for at least one of a timing violation, a timing variation, a voltage fluctuation, a parity error or an error correcting code error associated with the compute logic.

3. A method as defined in claim 1 wherein detecting a performance indicator associated with wearout of the compute logic comprises detecting that at least one of a monitored timing variation or a monitored voltage fluctuation exceeds a guard band.

4. A method as defined in claim 1 wherein controlling operation of the nanostore comprises reducing an operating speed of the compute logic until at least one of a monitored timing violation associated with the compute logic is reduced or a monitored timing variation associated with the compute logic is within a guard band.

5. A method as defined in claim 1 further comprising backing up at least one of data stored in the datastore or a summary of the data stored in the datastore after controlling the operation of the nanostore.

6. A method as defined in claim 1 further comprising:

monitoring performance of the nanostore to detect a second performance indicator associated with wearout of the datastore; and

controlling the operation of the compute logic to increase operating performance of the nanostore in response to determining that the wearout of the datastore is worse than the wearout of the compute logic.

7. A method as defined in claim 6 wherein monitoring performance of the nanostore to detect the second performance indicator comprises detecting an error associated with accessing the datastore.

8. A method as defined in claim 6 wherein controlling the operation of the nanostore to permit the compute logic to continue to access the datastore is in response to both detecting the performance indicator associated with the wearout of the compute logic and determining that the wearout of the compute logic is worse than the wearout of the datastore.

9. An apparatus comprising:

a monitor to monitor performance of compute logic and a datastore implementing a nanostore; and

a controller to;

determine wearout of the compute logic based on monitoring the performance of the compute logic;

determine wearout of the datastore based on monitoring the performance of the datastore; and

adjust operation of the compute logic based on a comparison of the wearout of the compute logic and the wearout of the datastore.

10. An apparatus as defined in claim 9 wherein the monitor is to:

monitor for at least one of a timing violation, a timing variation, a voltage fluctuation, a parity error or an error correcting code error associated with the compute logic to monitor the performance of the compute logic; and

monitor for an error associated with accessing the datastore to monitor the performance of the datastore.

11. An apparatus as defined in claim 9 wherein adjusting the operation of the compute logic comprises:

adjusting the operation of the compute logic to increase an operating speed of the nanostore in response to determining that the wearout of the datastore is worse than the wearout of the compute logic; and

adjusting the operation of the compute logic to reduce the operating speed of the nanostore in response to determining that the wearout of the datastore is worse than the wearout of the compute logic.

12. An apparatus as defined in claim 11 wherein adjusting the operation of the compute logic further comprises backing up at least one of data stored in the datastore or a summary of the data stored in the data store in response to determining that the wearout of the datastore is worse than the wearout of the compute logic and that the wearout of the compute logic exceeds a guard band.

13. A tangible article of manufacture storing machine readable instructions which, when executed, cause a machine to at least:

monitor performance of compute logic included in a nanostore, the nanostore including the compute logic and a datastore accessible via the compute logic;

determine a performance indicator associated with wearout of the compute logic based on monitoring the performance of the compute logic; and

back up at least one of data stored in the datastore or a summary of the data stored in the data store when wearout of the compute logic is predicted by the performance indicator.

14. A tangible article of manufacture as defined in claim 13 wherein the machine readable instructions, when executed, cause the machine to monitor for at least one of a timing violation, a timing variation, a voltage fluctuation, a parity error or an error correcting code error associated with the compute logic to monitor the performance of the compute logic.

15. A tangible article of manufacture as defined in claim 13 wherein the wearout of the compute logic is predicted by the performance indicator when the performance indicator indicates that a timing variation associated with the compute logic has been monitored, but the timing variation does not exceed a guard band.