TWO-PASS LINEAR COMPLEXITY TASK SCHEDULER
First Claim
1. A method for two-pass scheduling of a plurality of tasks, comprising the steps of:
- (A) assigning each of said tasks to a corresponding one or more of a plurality of processors in a first pass through said tasks, wherein said first pass is non-iterative;
(B) reassigning said tasks among said processors to shorten a respective load on one or more of said processors in a second pass through said tasks, wherein said second pass (i) is non-iterative and (ii) begins after said first pass has completed; and
(C) generating a schedule in response to said assigning and said reassigning, wherein said schedule maps said tasks to said processors.
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Abstract
A method for two-pass scheduling of a plurality of tasks generally including steps (A) to (C). Step (A) may assign each of the tasks to a corresponding one or more of a plurality of processors in a first pass through the tasks. The first pass may be non-iterative. Step (B) may reassign the tasks among the processors to shorten a respective load on one or more of the processors in a second pass through the tasks. The second pass may be non-iterative and may begin after the first pass has completed. Step (C) may generate a schedule in response to the assigning and the reassigning. The schedule generally maps the tasks to the processors.
13 Citations
20 Claims
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1. A method for two-pass scheduling of a plurality of tasks, comprising the steps of:
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(A) assigning each of said tasks to a corresponding one or more of a plurality of processors in a first pass through said tasks, wherein said first pass is non-iterative; (B) reassigning said tasks among said processors to shorten a respective load on one or more of said processors in a second pass through said tasks, wherein said second pass (i) is non-iterative and (ii) begins after said first pass has completed; and (C) generating a schedule in response to said assigning and said reassigning, wherein said schedule maps said tasks to said processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a memory configured to buffer a plurality of tasks; and a circuit configured to (i) assign each of said tasks to a corresponding one or more of a plurality of processors in a first pass through said tasks, wherein said first pass is non-iterative, (ii) reassign said tasks among said processors to shorten a respective load on one or more of said processors in a second pass through said tasks, wherein said second pass (i) is non-iterative and (ii) begins after said first pass has completed and (iii) generate a schedule in response to said assign and said reassign, wherein said schedule maps said tasks to said processors. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. An apparatus comprising:
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means for assigning each of a plurality of tasks to a corresponding one or more of a plurality of processors in a first pass through said tasks, wherein said first pass is non-iterative; means for reassigning said tasks among said processors to shorten a respective load on one or more of said processors in a second pass through said tasks, wherein said second pass (i) is non-iterative and (ii) begins after said first pass has completed; and means for generating a schedule in response to said assigning and said reassigning, wherein said schedule maps said tasks to said processors.
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Specification