SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON

• US 20120286356A1
• Filed: 07/26/2012
• Published: 11/15/2012
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hébert, François, Bhalla, Anup
• Granted Patent: US 8,703,563 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A method for manufacturing a semiconductor device comprising:

a) providing an N-type epitaxial (N-epi) layer;

b) forming a trench mask on top of the N-epi layer;

c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;

d) forming a gate oxide on a bottom and sidewalls of the trench;

e) filling a remaining space in the trench with a conductive material to form a gate electrode;

f) removing the trench mask;

g) implanting and diffusing dopants into a top region of the N-epi layer to form a P-body layer;

h) implanting and diffusing dopants into a top region of the P-body layer to form a source region;

i) forming oxide on top of the gate electrode and the source region;

j) etching portions of the oxide to expose selected portions of the source region;

k) etching selected portions of the source region not covered by the oxide down to the P-body layer;

l) depositing N+ doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and

m) etching back the N+ doped polysilicon to form an N+ doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.

2. The method of claim 1 wherein the conductive material is N+ doped polysilicon.

3. The method of claim 1 wherein c), d) and e) are implemented in a way that results in the conductive material of the gate electrode being recessed to below a surface of the N-epi layer.

4. The method of claim 1, further comprising, after m) doping an exposed portions of the P-body layer P+ to form a body contact region proximate the polysilicon spacer.

5. The method of claim 1, after step m, further comprising:

depositing barrier metal over the P-body layer, N+ doped polysilicon spacer and the oxide;

depositing and patterning a metal on top of the barrier metal; and

depositing and patterning a passivation layer on top of the patterned metal.

6. The method of claim 1, after step e, further comprising:

etching back the conductive material filled in the trench to a level below a top surface of the N-epi layer.

7. The method of claim 1, wherein step h) comprises implanting and diffusing dopants into the top region of the P-body layer to form an N+ source region.

8. The method of claim 1, wherein step h) comprises implanting and diffusing dopants into the top region of the P-body layer to form an N−

polysilicon source region.

9. The method of claim 1, after step k) further comprising etching a portion of a top surface of the P-body region not covered by the oxide to a level below that of a bottom surface of the source region.

10. A method for manufacturing a semiconductor device comprising:

a) providing an epitaxial layer of a first polarity type semiconductor;

b) forming a trench mask on top of the epitaxial layer;

c) etching the epitaxial layer through the trench mask to a predetermined depth to form a trench;

d) forming a gate oxide on a bottom and sidewalls of the trench;

e) filling a remaining space in the trench with a conductive material to form a gate electrode;

f) removing the trench mask;

g) implanting and diffusing dopants into a top region of an opposite polarity type to that of the epitaxial layer into the epitaxial layer to form a body layer of an opposite polarity to that of the epitaxial layer;

h) implanting and diffusing dopants into a top region of the body layer to form a source region;

i) forming oxide on top of the gate electrode and the source region;

j) etching portions of the oxide to expose selected portions of the source region;

k) etching selected portions of the source region not covered by the oxide down to the body layer;

l) depositing doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and

m) etching back the doped polysilicon to form a doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.

11. A semiconductor device comprising:

a body region formed in an epitaxial layer;

a gate electrode formed in a trench in the body region and epitaxial layer;

a source region disposed on the body region next to the gate electrode;

a gate oxide disposed between the gate electrode and the source region, the body region and the epitaxial layer;

a drain region formed by a substrate disposed below a bottom of the gate electrode and below the body region;

an oxide disposed on top of the gate electrode and extending over a top portion of the source region;

a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide;

an exposed body contact region in an upper portion of the body region, adjacent to the doped polysilicon spacer, wherein the exposed body contact region has a top surface which is recessed below the bottom surface of the source region and spaced away from the source region by the doped Polysilicon spacer; and

a source metal layer disposed on the device such that the doped polysilicon spacer is in electrical contact with the source region and the source metal layer.

12. The semiconductor device of claim 11, wherein a portion of a top surface of the body region not underlying the source region is recessed to a lower level than a portion of the top surface of the body region underlying the source region.

13. The semiconductor device of claim 11, wherein the doped polysilicon spacer extends to a top portion of the source region.

14. The semiconductor device of claim 11, wherein the semiconductor device is an N-channel device.