Liner Formation in 3DIC Structures

• US 20120289062A1
• Filed: 07/30/2012
• Published: 11/15/2012
• Est. Priority Date: 07/08/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Ching-Yu, Tu, Hung-Jung, Chen, Hai-Ching, Bao, Tien-I, Chiou, Wen-Chih, Yu, Chen-Hua
• Granted Patent: US 8,629,066 B2
• Time in Patent Office: Days
• US Class Current: 438/782
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

Claims

1. A method comprising:

forming an opening in a substrate; and

forming a liner dielectric in the opening, wherein the liner dielectric comprises a sidewall portion on a sidewall of the opening and a bottom portion on a bottom of the opening, and wherein thicknesses of the sidewall portion increase substantially continuously from top to bottom.

2. The method of claim 1, wherein the liner dielectric is formed using spin-on coating.

3. The method of claim 2, wherein the spin-on coating comprises:

placing the substrate with the opening facing up;

rotating the substrate with a first speed;

spraying a chemical on the substrate;

after the step of spraying the chemical, stopping rotating the substrate; and

after the step of stopping rotating the substrate, rotating the substrate with a second speed greater than the first speed.

4. The method of claim 3, wherein the first speed is between about 200 revolutions per minute (RPM) and about 250 RPM.

5. The method of claim 3, wherein a duration of the step of stopping rotating is greater than about 10 seconds.

6. The method of claim 3, wherein, at a time the chemical is sprayed on the substrate, an evaporation rate of the chemical is greater than about 3 pound per square inch (psi).

7. The method of claim 3, wherein the chemical comprises tetra-ethyl-ortho-silicate (TEOS) and methyltriethoxysilane (MTES).

8. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

forming a through-semiconductor via (TSV) opening in the substrate semiconductor; and

forming a TSV liner in the opening using spin-on coating, wherein the TSV liner comprises;

a sidewall portion on a sidewall of the opening; and

a bottom portion at a bottom of the opening, and wherein a top end of the TSV liner is lower than a top of the TSV opening.

9. The method of claim 8, wherein the bottom portion of the TSV liner has a thickness between about 5 percent and about 20 percent of a depth of the TSV opening.

10. The method of claim 8 further comprising grinding a portion of the semiconductor substrate, wherein the bottom portion of the TSV liner is removed.

11. The method of claim 8, wherein the step of forming the TSV liner comprises:

placing the semiconductor substrate with the TSV opening facing up;

rotating the semiconductor substrate with a first speed;

during the step of rotating the semiconductor substrate with the first speed, spraying a chemical on the semiconductor substrate;

after the step of spraying the chemical, reducing a rotating speed of the semiconductor substrate; and

after the step of reducing the rotating speed of the semiconductor substrate and with the chemical on the semiconductor substrate, rotating the semiconductor substrate with a second speed greater than the first speed.

12. The method of claim 11 further comprising, after the step of rotating the semiconductor substrate with the second speed, baking the semiconductor substrate to solidify the chemical.

13. The method of claim 11, wherein the first speed is between about 200 revolutions per minute (RPM) and about 250 RPM.

14. The method of claim 11, wherein the second speed is between 500 RPM and about 3,000 RPM.

15. The method of claim 11, wherein during the step of reducing the rotating speed of the semiconductor substrate, the semiconductor substrate is fully stopped from rotating.

16. The method of claim 11, wherein a duration of the step of stopping rotating is greater than about 10 seconds.

17. The method of claim 11, wherein an evaporation rate of the chemical is greater than about 3 pound per square inch (psi).

18. A method comprising:

forming an opening in a semiconductor substrate; and

forming a liner dielectric in the opening, wherein the liner dielectric comprises a sidewall portion on a sidewall of the opening and a bottom portion on a bottom of the opening, and wherein the step of forming the liner comprises;

placing the semiconductor substrate with the opening facing up;

rotating the semiconductor substrate with a first speed;

spraying a chemical on the semiconductor substrate;

after the step of spraying the chemical, stopping rotating the semiconductor substrate; and

after the step of stopping rotating the semiconductor substrate, rotating the semiconductor substrate with a second speed greater than the first speed.

19. The method of claim 18, wherein the first speed is between about 200 revolutions per minute (RPM) and about 250 RPM.

20. The method of claim 18, wherein a duration of the step of stopping rotating is greater than about 10 seconds.