Extremely Thin Semiconductor-On-Insulator (ETSOI) FET With A Back Gate and Reduced Parasitic Capacitance And Method of Forming The Same

• US 20120292700A1
• Filed: 05/16/2011
• Published: 11/22/2012
• Est. Priority Date: 05/16/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Khakifirooz, Ali, Cheng, Kangguo, Doris, Bruce B.
• Granted Patent: US 8,507,989 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel

Abstract

An extremely thin SOI MOSFET device on an SOI substrate is provided with a back gate layer on a Si substrate superimposed by a thin BOX layer; an extremely thin SOI layer (ETSOI) on top of the thin BOX layer; and an FET device on the ETSOI layer having a gate stack insulated by spacers. The thin BOX is formed under the ETSOI channel, and is provided with a thicker dielectric under source and drain to reduce the source/drain to back gate parasitic capacitance. The thicker dielectric portion is self-aligned with the gate. A void within the thicker dielectric portion is formed under the source/drain region. The back gate is determined by a region of semiconductor damaged by implantation, and the formation of an insulating layer by lateral etch and back filling with dielectric.

Claims

1. An extremely thin semiconductor-on-insulator (ETSOI) device comprising:

a. a back gate layer on a substrate superimposed by a thin BOX layer;

b. an extremely thin SOI layer on top of said thin BOX layer; and

c. an FET device on said extremely thin (ET) SOI layer having a gate stack insulated by spacers.

2. The ETSOI device recited in claim 1, wherein said thin BOX layer is formed underneath an ET SOI channel, and a thick dielectric underneath said source and drain, reducing the source and drain to back gate parasitic capacitance.

3. The ETSOI device recited in claim 1 further comprising a thick dielectric portion self-aligned with said FET gate.

4. The ETSOI device recited in claim 2 further comprising voids within said thick dielectric portion underneath said source and drain regions.

5. The ETSOI device recited in claim 1, wherein a back gate electrode includes a region of semiconductor damaged by an implantation, and an insulating layer laterally etched and back filled with dielectric.

6. The ETSOI device recited in claim 1, further comprising an etch region within said SOI substrate and backfilled with dielectric material.

7. The ETSOI device recited in claim 1 further comprising a plurality of active regions in said SOI layer and insulated using mesa insulation, LOCOS, or shallow-trench isolation (STI).

8. The ETSOI device recited in claim 4 further comprising a plurality of back gate regions underneath said active regions.

9. The ETSOI device recited in claim 8, wherein said plurality of back gate regions include implanted dopant ions into said substrate with sufficient energy to force dopant ions underneath said buried insulator.

10. The ETSOI device recited in claim 9, wherein said implanted dopants are activated to remove defects generated by said implantation.

11. The ETSOI device recited in claim 1 wherein different back gates are used for different active regions,

12. The ETSOI device recited in claim 7, wherein a shared back gate is used for more than one of said active region.

13. The ETSOI device recited in claim 1, wherein said back gate region has a thickness ranging between 20 and 200 nm, and an active dopant concentration greater than 1×

10¹⁸ cm<sup>−

3</sup>.

14. The ETSOI device recited in claim 7, wherein a plurality of gate dielectric, gate electrode, gate cap and spacer regions are formed within said active regions.

15. The ETSOI device recited in claim 1 further comprising modified regions within said substrate.

16. The ETSOI device recited in claim 15, wherein said modified regions are self-aligned with said gate and channel, and said gate is capped to protect said gate from ion implantation.

17. The ETSOI device recited in claim 15, wherein said modified regions include etching at a rate that exceeds the etching in an unmodified regions of said substrate.

18. The ETSOI device recited in claim 1 includes a single-crystalline silicon substrate implanted with Xe, As, or Ge.

19. A method of manufacturing an extremely thin SOI (ETSOI) device comprising:

a. providing a back gate layer on a Si substrate superimposed by a thin BOX layer;

b. forming said extremely thin SOI layer on top of said thin BOX layer; and

c. forming an FET device on said ETSOI layer, said FET having a gate stack insulated by spacers.

20. The method as recited in claim 19, further comprising forming a plurality of active regions in said SOI layer 20, said active regions being defined by lithography.

21. The method as recited in claim 19, wherein said active regions are isolated from each other by way of mesa isolation, LOCOS, or shallow-trench isolation (STI).

22. The method as recited in claim 19, further comprising forming a plurality of back gate regions underneath said active regions.

23. The method as recited in claim 19, wherein said plurality of regions are formed using implanting dopant ions into said substrate with an energy sufficient to place said dopant ions underneath said buried insulator.

24. The method as recited in claim 19, further comprising annealing to activate said dopants and remove defects generated by said implantation.

25. The method as recited in claim 19, further comprising different back gates for different active regions, wherein a shared back gate is used for both active regions.