Memory Arrays, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions

• US 20120299088A1
• Filed: 05/27/2011
• Published: 11/29/2012
• Est. Priority Date: 05/27/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Surthi, Shyam, Guha, Jaydip, Heineck, Lars P.
• Granted Patent: US 8,569,831 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7788 Vertical transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/488 Word lines

Abstract

Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting transistors along columns of the array. Each individual transistor may be directly over only a single digit line, with the single digit line being entirely composed of one or more metal-containing materials. The digit lines can be over a deck, and electrically insulative regions can be directly between the digit lines and the deck. Some embodiments include methods of forming memory arrays. A plurality of linear segments of silicon-containing material may be formed to extend upwardly from a base of the silicon-containing material. The base may be etched to form silicon-containing footings under the linear segments, and the footings may be converted into metal silicide. The linear segments may be patterned into a plurality of vertically-oriented transistor pedestals that extend upwardly from the metal silicide footings.

Claims

1. A memory array having rows and columns, comprising:

digit lines under vertically-oriented transistors;

the digit lines interconnecting the transistors along columns of the array and being entirely composed of one or more metal-containing materials;

the vertically-oriented transistors having bottom source/drain regions electrically coupled to the digit lines;

wherein the digit lines are over a semiconductor deck comprising semiconductor material; and

wherein electrically insulative regions are directly between the digit lines and the semiconductor material of the deck.

2. The memory array of claim 1 wherein individual digit lines have memory array sections that interconnect the transistors along the columns of the array, and have other sections peripheral to the memory array sections, and wherein the electrically insulative regions are lines extending full lengths of the memory array sections of the individual digit lines.

3. The memory array of claim 1 wherein the electrically insulative regions include gas-filled cavities.

4. The memory array of claim 1 wherein the electrically insulative regions are entirely electrically insulative material which is at least semisolid.

5. The memory array of claim 1 wherein the vertically-oriented transistors comprise semiconductor material pedestals, and wherein the digit lines comprise metal/semiconductor material directly against semiconductor material of the semiconductor material pedestals.

6. The memory array of claim 1 wherein the vertically-oriented transistors comprise silicon-containing pedestals, and wherein the digit lines comprise metal silicide directly against silicon of the silicon-containing pedestals.

7. The memory array of claim 1 further comprising metal-containing material directly between the electrically insulative regions and the semiconductor material of the deck.

8. A semiconductor construction, comprising:

an array of vertically-oriented transistors;

individual of the transistors comprising a bottom source/drain region, a top source/drain region, and a channel region between the top and bottom source/drain regions;

the array comprising rows and columns;

access lines extending along rows of the array to interconnect transistors along said rows, the access lines extending across the channel regions and forming gates across the transistors to gatedly couple the top and bottom source/drain regions through the channel regions;

digit lines extending along columns of the array to interconnect transistors along said columns, the digit lines being electrically coupled to the bottom source/drain regions of the transistors and being comprised entirely of one or more metal-containing materials; and

each transistor of the array being uniquely addressed by a combination of an access line and a digit line.

9. The semiconductor construction of claim 8 further comprising metal/semiconductor material directly against the bottom source/drain regions;

and wherein the digit lines comprise a metal-containing composition directly against the metal/semiconductor material.

10. The semiconductor construction of claim 9 wherein the metal/semiconductor material is metal silicide.

11. The semiconductor construction of claim 9 wherein the metal/semiconductor material is configured as lines that are part of the digit lines.

12. The semiconductor construction of claim 9 wherein the metal/semiconductor material is configured as separated blocks associated with the individual transistors.

13. The semiconductor construction of claim 9 wherein the metal-containing composition comprises metal nitride, elemental metal, or mixtures of two or more metals.

14. The semiconductor construction of claim 8 wherein the digit lines directly contact semiconductor material of a deck directly under the digit lines;

the semiconductor material directly under the digit lines being first doped stripes doped to a first dopant type;

the semiconductor construction further comprising second doped stripes directly between the first doped stripes and doped to a second dopant type opposite to the first dopant type.

15. The semiconductor construction of claim 8 wherein the semiconductor deck contains semiconductor material directly under the digit lines;

the semiconductor construction further comprising electrically insulative regions between the digit lines and the semiconductor material of the deck that is directly under the digit lines.

16. The semiconductor construction of claim 15 wherein the electrically insulative regions include gas-filled cavities.

17. The semiconductor construction of claim 15 wherein the electrically insulative regions are entirely electrically insulative material which is at least semisolid.

18. A method of forming a semiconductor construction, comprising:

patterning a semiconductor material to form a plurality of linear segments of the semiconductor material extending upwardly from a base of the semiconductor material, the segments being spaced from one another by intervening trenches;

individual linear segments comprising sidewall surfaces;

forming protective material along the sidewall surfaces;

etching into the base to form cavities under the linear segments;

forming metal-containing lines within the cavities;

patterning each of the linear segments into a plurality of vertically-oriented transistor pedestals;

the transistor pedestals extending upwardly from the metal-containing lines;

the transistor pedestals forming an array comprising rows and columns;

the metal-containing lines extending along columns of the array to interconnect transistor pedestals along said columns, and the metal-containing lines thus being incorporated into digit lines;

the digit lines only comprising metal-containing materials; and

forming access lines extending along rows of the array to interconnect transistor pedestals along said rows.

19. The method of claim 18 further comprising forming top and bottom source/drain regions within the individual transistor pedestals, with the top and bottom source/drain regions of individual transistor pedestals being spaced from one another by channel regions within the individual transistor pedestals.

20. The method of claim 19 wherein the bottom source/drain regions are formed by implanting dopant into bottoms of the linear segments prior to forming the metal-containing lines.

21. The method of claim 19 wherein the top source/drain regions are formed by implanting dopant into tops of the transistor pedestals after forming the access lines.

22. The method of claim 18 wherein the cavities completely undercut the linear segments to convert the segments into bridges having gaps thereunder, wherein the metal-containing lines are formed along the bottoms of the bridges and do not eliminate the gaps under the bridges, and wherein the patterning of the segments into the vertically-oriented transistor pedestals comprises patterning the bridges into the vertically-oriented transistor pedestals.

23. The method of claim 22 further comprising filling the gaps under the bridges with electrically insulative material after forming the metal-containing lines, with said electrically insulative material being at least semisolid.

24. The method of claim 22 wherein gas-filled gaps remain under the metal-containing lines after forming the access lines.

25. The method of claim 18 wherein the semiconductor material comprises silicon;

wherein the cavities extend only partially under the linear segments to leave silicon-containing footings under the linear segments; and

further comprising converting the silicon of the silicon-containing footings into metal silicide by reacting silicon from the silicon-containing footings with metal from the metal-containing lines.

26. A method of forming a semiconductor construction, comprising:

patterning a semiconductor material to form a plurality spaced-apart bridges of the semiconductor material extending over a deck, the bridges being spaced from the deck by gaps;

forming metal-containing lines along undersides of the bridges, the metal-containing lines not completely filling the gaps under the bridges;

patterning each of the bridges into a plurality of vertically-oriented transistor pedestals;

the transistor pedestals extending upwardly from the metal-containing lines;

the transistor pedestals forming an array comprising rows and columns;

the metal-containing lines extending along columns of the array to interconnect transistor pedestals along said columns; and

forming access lines extending along rows of the array to interconnect transistor pedestals along said rows.

27. The method of claim 26 further comprising doping the semiconductor material along the bottoms of the bridges prior to forming the metal-containing lines.

28. The method of claim 26 further comprising filling the gaps under the bridges with electrically insulative material after forming the metal-containing lines, with said electrically insulative material being at least semisolid.

29. The method of claim 26 wherein gas-filled gaps remain under the metal-containing lines after forming the access lines.

30. A method of forming a semiconductor construction, comprising:

patterning a silicon-containing material to form a plurality of linear segments of the silicon-containing material extending upwardly from a base of the silicon-containing material, the segments being spaced from one another by intervening trenches;

individual linear segments comprising sidewall surfaces;

forming protective material along the sidewall surfaces;

etching into the base to form silicon-containing footings under the linear segments;

converting the footings into metal silicide;

patterning each of the linear segments into a plurality of vertically-oriented transistor pedestals;

the transistor pedestals extending upwardly from the metal silicide footings;

forming top and bottom source/drain regions within the transistor pedestals, with the top and bottom source/drain regions of individual pedestals being spaced from one another by channel regions within the individual pedestals;

the transistor pedestals forming an array comprising rows and columns;

the metal silicide footings extending along columns of the array to interconnect transistor pedestals along said columns; and

forming access lines extending along rows of the array to interconnect transistor pedestals along said rows, the access lines extending across the channel regions and forming gates across the channel regions.

31. The method of claim 30 wherein the metal silicide footings are utilized as digit lines extending under the array, and wherein the metal silicide of the footings is the only electrically conductive material of the digit lines under the array.

32. The method of claim 30 further comprising forming metal-containing lines on opposing sides of individual metal silicide footings to form digit lines comprising the footings in combination with the metal-containing lines.

33. The method of claim 30 wherein the protective material is electrically insulative, and remains along sidewalls of the transistor pedestals as gate dielectric.

34. The method of claim 30 further comprising removing the protective material and replacing it with gate dielectric.