DATA PROCESSING METHOD, DATA PROCESSOR AND APPARATUS INCLUDING A DATA PROCESSOR

• US 20120304024A1
• Filed: 02/16/2010
• Published: 11/29/2012
• Est. Priority Date: 02/16/2010
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rohleder, Michael, Fader, Joachim, Lenke, Frank, Baumeister, Markus
• Granted Patent: US 9,052,887 B2
• Time in Patent Office: Days
• US Class Current: 714/49
• CPC Class Codes: G06F 11/1645 and the comparison itself uses redundant hardware
• CPC Class Codes: G06F 11/1695 which are operating with time diversity
• CPC Class Codes: G06F 2201/845 Systems in which the redundancy can be transformed in increased performance
• CPC Class Codes: G06F 9/28 Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead

Abstract

A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.

Claims

1. A method of processing data in a data processor comprising at least two data processing units, the method comprising:

performing different data processing steps in said data processing units concurrently during a parallel operation, and

replicating performances of selected identical data processing steps in said data processing units during a non-synchronised redundant operation, said non-synchronised redundant operation comprising an initial performance of said selected identical data processing steps, a replicate performance of said data processing steps starting later than said initial performance, registering initial result data representative of results from said initial performance of said selected identical data processing steps, comparing replicate result data representative of results from said replicate performance of said selected identical data processing steps with said initial result data, and producing an error signal in case of discrepancy between said replicate result data and said initial result data.

2. A method of processing data as claimed in claim 1, wherein said replicating performances of selected identical data processing steps comprises an initial performance of said selected identical data processing steps in one of said data processing units and a replicate performance of said data processing steps in another of said data processing units.

3. A method of processing data as claimed in claim 1, wherein said parallel operation or said non-synchronised redundant operation is selected as a function of position in a sequence of said data processing steps or of a memory address for said data processing steps.

4. A method of processing data as claimed in claim 1, wherein said parallel operation and said non-synchronised redundant operation have durations corresponding to durations of operating system tasks and/or software threads, whereby to enable a granularity of switching between said parallel operation and said non-synchronised redundant operation to correspond with said durations of operating system tasks and/or software threads.

5. A method of processing data as claimed in claim 1, wherein said redundant operation starts and terminates in response to a start instruction key and a termination instruction key, respectively.

6. A method of processing data as claimed in claim 1, wherein said redundant operation starts and terminates in response to a specific start operation address and a specific termination operation address, respectively.

7. A method of processing data as claimed in claim 1, wherein at least volatile data accessed during said initial performance of said selected identical data processing steps is recorded and the recorded data is used in said replicate performance of said data processing steps.

8. A method of processing data as claimed in claim 7, wherein volatile data recorded in said initial performance of said redundant operation replaces volatile data for use in said replicate performance, and/or volatile data used in said replicate performance is verified against volatile data recorded in said initial performance of said redundant operation, and/or modifications of volatile data in said replicate performance are prevented.

9. (canceled)

10. (canceled)

11. (canceled)

12. (canceled)

13. (canceled)

14. (canceled)

15. (canceled)

16. (canceled)

17. (canceled)

18. A data processor comprising at least two data processing units, said data processing units being arranged to perform different data processing steps concurrently during a parallel operation, and alternatively to replicate performances of selected identical data processing steps during a non-synchronised redundant operation, said data processing units including at least one comparison module operational during said non-synchronised redundant operation to register initial result data representative of results from an initial performance of said selected identical data processing steps in a first one of said data processing units, to produce replicate result data representative of results from a replicate performance of said data processing steps starting later than said initial performance in a second one of said data processing units, to compare said replicate result data with said initial result data, and to produce an error signal in case of discrepancy between said replicate result data and said initial result data.

19. A data processor as claimed in claim 18, wherein said data processing units are arranged to execute said initial performance of said selected identical data processing steps in one of said data processing units and a replicate performance of said data processing steps in another of said data processing units.

20. A data processor as claimed in claim 18, wherein said data processing units are operable to perform data processing steps with different clock speeds during said parallel operation and said non-synchronised redundant operation.

21. A data processor as claimed in claim 18, wherein said at least one comparison module is arranged to be non operational during said parallel operation.

22. A data processor as claimed in claim 18, wherein said at least one comparison module includes a data store for recording at least volatile data accessed in said initial performance of said selected identical data processing steps, said replicate performance of said data processing steps being arranged to use data stored in said data store.

23. A data processor as claimed in claim 22, wherein said replicate performance of said data processing steps is arranged to replace volatile data for use in said replicate performance with volatile data recorded in said initial performance of said redundant operation, and/or to verify volatile data recorded in said initial performance of said redundant operation against volatile data used in said replicate performance, and/or to prevent modifications of volatile data in said replicate performance.

24. A data processor as claimed in claim 18, wherein said at least one comparison module is arranged to register and compare hash codes condensing at least a portion of non-volatile data used in said initial performance and said replicate performance.

25. A data processor as claimed in claim 18, wherein said at least one comparison module includes one or more record/retrieve units operational to register an initial hash code of data included in said initial result data produced by said first one of said data processing units, and to compare a replicate hash code of data included in said replicate result data produced by said second one of said data processing units, said at least one comparison module being arranged to compare said replicate hash code with said initial hash code, and to produce an error signal in case of discrepancy between said replicate hash code and said initial hash code.

26. A data processor as claimed in claim 25, wherein said at least one comparison module includes a plurality of comparison elements at least one of which is operable to receive said initial hash code or said replicate hash code from another of said comparison elements, to compare said replicate hash code with said initial hash code, and to produce an error signal in case of discrepancy between said replicate hash code and said initial hash code.

27. A data processor as claimed in claim 26, wherein any one of said comparison elements is operable to compute and register said initial hash code, the other comparison element or elements being arranged to be activated subsequently to compute said replicate hash code.

28. A data processor as claimed in claim 25, wherein said at least one comparison module is operable in said redundant mode to produce said initial result data and said replicate result data as a function at least of said results from an initial performance or of said results from a replicate performance respectively and also of data including one or more of the following:

instruction codes, instruction addresses, write and read data and addresses, and system status information.

29. Apparatus comprising a data processor as claimed in claim 18, sensors for sending data to said data processor and actuators connected to be controlled by said data processor.