METHOD AND SYSTEM FOR INTERNAL LAYER-LAYER THERMAL ENHANCEMENT

• US 20120306088A1
• Filed: 06/02/2011
• Published: 12/06/2012
• Est. Priority Date: 06/02/2011
• Status: Active Grant

• Current Assignee: Lenovo International Limited (Lenovo Group Ltd.)
• Original Assignee: International Business Machines Corporation
• Inventors: BARTLEY, Gerald K., JOHNSON, Charles L., KELLY, John E. III, MOTSCHMAN, David R.
• Granted Patent: US 8,367,478 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/4275 by melting or evaporation of solids
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body

Abstract

The exemplary embodiments of the present invention provide a method and apparatus for enhancing the cooling of a chip stack of semiconductor chips. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes creating a cavity in a second side of the first chip between the connectors and filling the cavity with a thermal material. The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.

Claims

1. A method for enhancing the cooling of a chip stack of semiconductor chips, comprising:

creating a first chip with circuitry on a first side;

creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors;

creating a cavity in a second side of the first chip between the connectors; and

filling the cavity with a thermal material.

2. The method of claim 1, wherein the cavity is created by removing material from the first chip.

3. The method of claim 2, wherein the cavity is created using an etching process.

4. The method of claim 2, wherein the cavity is created using a milling process.

5. The method of claim 1, wherein the thermal material is a thermal grease that includes a conductive particulate.

6. The method of claim 1, wherein the thermal material comprises:

a first thermal filler material used to fill a lower portion of the cavity; and

a second thermal filler material used to fill an upper portion of the cavity.

7. The method of claim 6, wherein the first thermal filler material in the cavity is electrically isolated from the grid of connectors.

8. A system for enhancing the cooling of a chip stack of semiconductor chips, comprising:

a means for creating a first chip with circuitry on a first side;

a means for creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors;

a means for creating a cavity in a second side of the first chip between the connectors; and

a means for filling the cavity with a thermal material.

9. The system of claim 8, wherein the means for creating cavity is created by a means for removing material from the first chip.

10. The system of claim 8, wherein the means for creating cavity is an etching process.

11. The system of claim 8, wherein the means for creating cavity is a milling process.

12. The system of claim 8, wherein the thermal material is a thermal grease that includes a conductive particulate.

13. The system of claim 8, wherein the thermal material comprises:

a first thermal filler material used to fill a lower portion of the cavity; and

a second thermal filler material used to fill an upper portion of the cavity.

14. The system of claim 13, wherein the first thermal filler material in the cavity is electrically isolated from the grid of connectors.

15. A chip stack of semiconductor chips with enhanced cooling comprising:

a first chip with circuitry on a first side;

a second chip electrically and mechanically coupled to the first chip by a grid of connectors; and

wherein portions of a second side of the first chip between the connectors is removed to provide a cavity in which a thermal material is placed.

16. The apparatus of claim 15, wherein the cavity is created using an etching process.

17. The apparatus of claim 15, wherein the cavity is created using a milling process.

18. The apparatus of claim 15, wherein the thermal material is a thermal grease that includes a conductive particulate.

19. The apparatus of claim 15, wherein the thermal material comprises:

a first thermal filler material used to fill the lower portion of the cavity; and

a second thermal filler material used to fill the upper portion of the cavity.

20. The apparatus of claim 19, wherein the first thermal filler material in the cavity is electrically isolated from the grid of connectors.