FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION

• US 20120313168A1
• Filed: 06/08/2011
• Published: 12/13/2012
• Est. Priority Date: 06/08/2011
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: DORIS, Bruce B., KHAKIFIROOZ, Ali, KULKARNI, Pranita, SHAHIDI, Ghavam G., CHENG, Kangguo
• Granted Patent: US 8,536,032 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

Claims

1. An extremely-thin silicon-on-insulator transistor comprising:

a buried oxide layer above a substrate;

a silicon layer above the buried oxide layer;

a gate stack on the silicon layer comprising at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric; and

a gate spacer having a first part on the silicon layer, and a second part adjacent to the gate stack;

a first raised source/drain region and a second raised source/drain region each having a first part comprising a portion of the silicon layer and a second part adjacent to the gate spacer; and

at least one embedded stressor formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

2. The extremely-thin silicon-on-insulator of claim 1, wherein the at least one embedded stressor is formed entirely within the substrate.

3. The extremely-thin silicon-on-insulator of claim 1, wherein the buried oxide layer comprises a thickness that is less than 50 nm.

4. The extremely-thin silicon-on-insulator of claim 1, wherein the silicon layer comprises a thickness ranging from 2 nm-15 nm.

5. The extremely-thin silicon-on-insulator of claim 1, wherein the at least one embedded stressor comprises a silicon-germanium, silicon-tin, or silicon-germanium-tin alloy.

6. The extremely-thin silicon-on-insulator of claim 1, wherein the at least one embedded stressor comprises a silicon-carbon alloy.

7. The extremely-thin silicon-on-insulator of claim 1, wherein the at least one embedded stressor comprises a first embedded stressor substantially aligned with the first raised source/drain region and a second embedded stressor substantially aligned with the second raised source/drain region.

8. The extremely-thin silicon-on-insulator of claim 1, wherein the at least one embedded stressor is substantially aligned with the gate stack.

9. A method for fabricating an extremely-thin-silicon-on-insulator transistor, the method comprising:

forming a buried oxide layer on a silicon substrate;

forming a silicon layer on the buried oxide layer;

forming a gate stack on the silicon layer that is above the buried oxide layer;

forming a gate spacer on the silicon layer and on sidewalls of the gate stack;

epitaxially forming a first raised source/drain region and a second raised source/drain region each adjacent to the gate spacer; and

forming at least one embedded stressor at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

10. The method of claim 9, wherein the at least one embedded stressor is formed after the gate stack is formed with a gate dielectric on the silicon layer and a gate conductor on the gate dielectric, and prior to forming the first and second raised source/drain regions, wherein forming the at least one embedded stressor comprises:

forming at least one amorphized implant region at least partially within the substrate, wherein the at least one amorphized implant region comprises one of implanted germanium, implanted tin, and implanted carbon; and

recrystallizing the one of implanted germanium, implanted tin, and implanted carbon of the at least one amorphized implant region, the recrystallizing forming one of a silicon-germanium alloy, silicon-tin, or silicon-germanium-tin and a silicon-carbon alloy, respectively.

11. The method of claim 10, wherein the at least one germanium and tin is formed by one of a vertical implantation process and an angled implantation process.

12. The method of claim 9, wherein the gate stack is a replacement gate stack, and wherein forming the at least one embedded stressor comprises:

forming a dielectric layer on the first and second raised source/drain regions, the gate spacer, and the replacement gate stack;

removing the replacement gate stack exposing a portion of a top surface of the silicon layer between a first vertical wall and a second vertical wall of the gate spacer;

implanting one of germanium, tin, and carbon at least partially within the substrate through the portion of the top surface of the silicon layer, the implanting forming at least one amorphized implant region at least partially within the substrate comprising the one of germanium, tin, and carbon; and

recrystallizing the one of germanium, tin, and carbon that has been implanted at least partially within the substrate, the recrystallizing forming one of a silicon-germanium alloy, silicon-tin, or silicon-germanium-tin and a silicon-carbon alloy, respectively.

13. The method of claim 9, further comprising:

masking at least a gate stack and a silicon layer formed on a buried oxide layer of a corresponding transistor device as the at least one embedded stressor is being formed.

14. The method of claim 9, wherein the buried oxide layer is formed with a thickness that is less than 50 nm.

15. The method of claim 9, wherein the silicon layer is formed with a thickness ranging from 2 nm-15 nm.

16. The method of claim 9, wherein the at least one embedded stressor comprises a first embedded stressor substantially aligned with the first raised source/drain region and a second embedded stressor substantially aligned with the second raised source/drain region.

17. The method of claim 9, wherein the at least one embedded stressor is substantially aligned with the gate stack.

18. An integrated circuit comprising:

a circuit supporting substrate having an electrical circuit disposed thereon; and

an extremely-thin silicon-on-insulator transistor comprising;

a buried oxide layer above a substrate;

a silicon layer above the buried oxide layer;

a gate stack on the silicon layer comprising at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric; and

a gate spacer having a first part on the silicon layer, and a second part adjacent to the gate stack;

a first raised source/drain region and a second raised source/drain region each having a first part comprising a portion of the silicon layer and a second part adjacent to the gate spacer; and

at least one embedded stressor formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

19. The integrated circuit of claim 18, wherein the at least one embedded stressor comprises a first embedded stressor formed within the substrate and substantially aligned with the first raised source/drain region and a second embedded stressor formed within the substrate and substantially aligned with the second raised source/drain region.

20. The integrated circuit of claim 18, wherein the at least one embedded stressor is formed within the substrate and is substantially aligned with the gate stack.