SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM

• US 20120317328A1
• Filed: 08/21/2012
• Published: 12/13/2012
• Est. Priority Date: 05/10/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Rankin, Linda J., Pierce, Paul R., Dermer, Gregory E., Wang, Wen-Hann, Cheng, Kai, Hofsheier, Richard H., Borkar, Nitin Y.
• Granted Patent: US 8,745,306 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

Claims

1. An apparatus comprising:

a crossbar router;

a bridge communicatively coupled to the crossbar router, the bridge including a data buffer to hold data associated with write request or read completion; and

a Direct Memory Access (DMA) engine coupled to the crossbar router.

2. The apparatus of claim 1 further comprises a mapping register accessible by the bridge, the mapping register to provide route information to the bridge.

3. The apparatus of claim 2, wherein the bridge to obtain the route information for converting point-to-point request to X-Link request.

4. The apparatus of claim 1 further comprises an internal bus interface unit (BIU) coupled to the DMA engine and the crossbar router.

5. The apparatus of claim 1, wherein the data buffer is managed according to point-to-point bus rules and X-Link rules.

6. The apparatus of claim 1, wherein the bridge to manage request queues and the data buffers.

7. The apparatus of claim 1, wherein the crossbar router supports multiple virtual channels on an X-Link.

8. The apparatus of claim 1, wherein the crossbar router to examine route information received at its entrance port and to determine an exit port.

9. The apparatus of claim 1, wherein the DMA engine to generate memory read request.

10. The apparatus of claim 1, wherein the DMA engine to identify isochronous transfers and to control bandwidth allocation of X-Links.

11. A multiprocessor system comprising:

a processing module;

an input-output (I/O) module; and

an interconnect network for coupling the processing module to the I/O module, the interconnect network comprising a bridge to determine destination of a transaction between the processing module and the I/O module via a route lookup table.

12. The multiprocessor system of claim 11, wherein the route lookup table to accommodate a memory mapped I/O organization.

13. The multiprocessor system of claim 11, wherein the bridge is operable to communicate via a point-to-point bus protocol.

14. The multiprocessor system of claim 11, wherein the processing module includes a plurality of processor cores, a memory, and a memory controller.

15. A multiprocessor system comprising:

a processing module;

an input-output (I/O) module; and

an interconnect network for coupling the processing module to the I/O module, the interconnect network comprising a crossbar switch to route transactions associated with the processing module and the I/O module.

16. The multiprocessor system of claim 15, wherein the crossbar switch is a high bandwidth multi-ported non-blocking switch.

17. The multiprocessor system of claim 15, wherein the crossbar switch is in a mesh topology.

18. The multiprocessor system of claim 15, wherein the crossbar switch has a clock source independent of the clock source of the processing module.

19. The multiprocessor system of claim 15, wherein the processing module includes a plurality of processor cores, a memory, and a memory controller.

20. The multiprocessor system of claim 15, wherein the crossbar switch to support independent power/on and reset functions.